[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20200714190945.GD3008823@iweiny-DESK2.sc.intel.com>
Date: Tue, 14 Jul 2020 12:09:45 -0700
From: Ira Weiny <ira.weiny@...el.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Andy Lutomirski <luto@...nel.org>,
Fenghua Yu <fenghua.yu@...el.com>, x86@...nel.org,
Dave Hansen <dave.hansen@...ux.intel.com>,
Dan Williams <dan.j.williams@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
Andrew Morton <akpm@...ux-foundation.org>,
linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-nvdimm@...ts.01.org, linux-fsdevel@...r.kernel.org,
linux-mm@...ck.org, linux-kselftest@...r.kernel.org
Subject: Re: [RFC PATCH 04/15] x86/pks: Preserve the PKRS MSR on context
switch
On Tue, Jul 14, 2020 at 09:05:39PM +0200, Peter Zijlstra wrote:
> On Tue, Jul 14, 2020 at 11:53:22AM -0700, Ira Weiny wrote:
> > On Tue, Jul 14, 2020 at 10:27:01AM +0200, Peter Zijlstra wrote:
> > > On Tue, Jul 14, 2020 at 12:02:09AM -0700, ira.weiny@...el.com wrote:
> > > > From: Ira Weiny <ira.weiny@...el.com>
> > > >
> > > > The PKRS MSR is defined as a per-core register. This isolates memory
> > > > access by CPU. Unfortunately, the MSR is not preserved by XSAVE.
> > > > Therefore, We must preserve the protections for individual tasks even if
> > > > they are context switched out and placed on another cpu later.
> > >
> > > This is a contradiction and utter trainwreck.
> >
> > I don't understand where there is a contradiction? Perhaps I should have said
> > the MSR is not XSAVE managed vs 'preserved'?
>
> You're stating the MSR is per-*CORE*, and then continue to talk about
> per-task state.
>
> We've had a bunch of MSRs have exactly that problem recently, and it's
> not fun. We're not going to do that again.
Ah sorry, my mistake yes I meant 'per-logical-processor' like Dave said. I'll
update the commit message.
Ira
Powered by blists - more mailing lists