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Message-Id: <1594811350-14066-18-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Wed, 15 Jul 2020 12:09:07 +0100
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
Wolfram Sang <wsa+renesas@...g-engineering.com>,
Rob Herring <robh+dt@...nel.org>,
Wolfgang Grandegger <wg@...ndegger.com>,
Marc Kleine-Budde <mkl@...gutronix.de>,
"David S. Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Mark Brown <broonie@...nel.org>,
Niklas <niklas.soderlund@...natech.se>,
Zhang Rui <rui.zhang@...el.com>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck <linux@...ck-us.net>,
Magnus Damm <magnus.damm@...il.com>
Cc: Daniel Lezcano <daniel.lezcano@...aro.org>,
Amit Kucheria <amit.kucheria@...durent.com>,
Thomas Gleixner <tglx@...utronix.de>,
Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>,
linux-i2c@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-can@...r.kernel.org,
netdev@...r.kernel.org, linux-spi@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, linux-pm@...r.kernel.org,
linux-watchdog@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 17/20] arm64: dts: renesas: r8a774e1: Add RWDT node
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G2H (r8a774e1) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@...renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index 03e5982b8456..b2fa1a60470c 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -290,10 +290,14 @@
ranges;
rwdt: watchdog@...20000 {
+ compatible = "renesas,r8a774e1-wdt",
+ "renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
status = "disabled";
-
- /* placeholder */
};
gpio0: gpio@...50000 {
--
2.17.1
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