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Message-Id: <20200716145201.186270-2-arnaud.ferraris@collabora.com>
Date: Thu, 16 Jul 2020 16:52:00 +0200
From: Arnaud Ferraris <arnaud.ferraris@...labora.com>
To: alsa-devel@...a-project.org
Cc: Timur Tabi <timur@...nel.org>,
Nicolin Chen <nicoleotsuka@...il.com>,
Xiubo Li <Xiubo.Lee@...il.com>,
Fabio Estevam <festevam@...il.com>,
Shengjiu Wang <shengjiu.wang@...il.com>,
Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>, linux-kernel@...r.kernel.org,
kernel@...labora.com,
Arnaud Ferraris <arnaud.ferraris@...labora.com>
Subject: [PATCH 1/2] ASoC: fsl_asrc: make sure the input and output clocks are different
The current clock selection algorithm might select the same clock for
both input and output. This can happen when, for instance, the output
sample rate is a multiple of the input rate.
This patch makes sure it always selects distinct input and output
clocks.
Signed-off-by: Arnaud Ferraris <arnaud.ferraris@...labora.com>
---
sound/soc/fsl/fsl_asrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c
index 02c81d2e34ad..bfd35b9c0781 100644
--- a/sound/soc/fsl/fsl_asrc.c
+++ b/sound/soc/fsl/fsl_asrc.c
@@ -622,7 +622,8 @@ static void fsl_asrc_select_clk(struct fsl_asrc_priv *asrc_priv,
clk_rate = clk_get_rate(asrc_priv->asrck_clk[clk_index]);
/* Only match a perfect clock source with no remainder */
if (clk_rate != 0 && (clk_rate / rate[j]) <= 1024 &&
- (clk_rate % rate[j]) == 0)
+ (clk_rate % rate[j]) == 0 &&
+ (j == 0 || i != select_clk[j-1]))
break;
}
--
2.27.0
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