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Message-ID: <20200717030203.14872-3-huihui.wang@mediatek.com>
Date: Fri, 17 Jul 2020 11:02:05 +0800
From: Huihui Wang <huihui.wang@...iatek.com>
To: Sean Wang <sean.wang@...iatek.com>, Vinod Koul <vkoul@...nel.org>,
"Rob Herring" <robh+dt@...nel.org>
CC: <linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<wsd_upstream@...iatek.com>, huihui wang <huihui.wang@...iatek.com>
Subject: [PATCH v1 2/2] dma: mediatek: dma address bits config with compatible data
From: huihui wang <huihui.wang@...iatek.com>
1.Legacy implement only support 33 bits address,
we change the solution to support any width address.
2.DMA address bits is very detail information,
and it is not proper to config in device tree.
So we move it into mtk_uart_apdma.c,
and config it by compatible data.
Signed-off-by: huihui wang <huihui.wang@...iatek.com>
---
drivers/dma/mediatek/mtk-uart-apdma.c | 55 +++++++++++++++++++--------
1 file changed, 40 insertions(+), 15 deletions(-)
diff --git a/drivers/dma/mediatek/mtk-uart-apdma.c b/drivers/dma/mediatek/mtk-uart-apdma.c
index 29f1223b285a..9c080f9917a7 100644
--- a/drivers/dma/mediatek/mtk-uart-apdma.c
+++ b/drivers/dma/mediatek/mtk-uart-apdma.c
@@ -31,7 +31,6 @@
#define VFF_EN_B BIT(0)
#define VFF_STOP_B BIT(0)
#define VFF_FLUSH_B BIT(0)
-#define VFF_4G_EN_B BIT(0)
/* rx valid size >= vff thre */
#define VFF_RX_INT_EN_B (BIT(0) | BIT(1))
/* tx left size >= vff thre */
@@ -43,7 +42,7 @@
#define VFF_EN_CLR_B 0
#define VFF_INT_EN_CLR_B 0
#define VFF_4G_SUPPORT_CLR_B 0
-
+#define VFF_ORI_ADDR_BITS_NUM 32
/*
* interrupt trigger level for tx
* if threshold is n, no polling is required to start tx.
@@ -75,10 +74,14 @@
#define VFF_DEBUG_STATUS 0x50
#define VFF_4G_SUPPORT 0x54
+struct mtk_uart_apdmacomp {
+ unsigned int addr_bits;
+};
+
struct mtk_uart_apdmadev {
struct dma_device ddev;
struct clk *clk;
- bool support_33bits;
+ unsigned int support_bits;
unsigned int dma_requests;
};
@@ -152,8 +155,9 @@ static void mtk_uart_apdma_start_tx(struct mtk_chan *c)
mtk_uart_apdma_write(c, VFF_WPT, 0);
mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
- if (mtkd->support_33bits)
- mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B);
+ if (mtkd->support_bits > VFF_ORI_ADDR_BITS_NUM)
+ mtk_uart_apdma_write(c, VFF_4G_SUPPORT,
+ upper_32_bits(d->addr));
}
mtk_uart_apdma_write(c, VFF_EN, VFF_EN_B);
@@ -195,8 +199,9 @@ static void mtk_uart_apdma_start_rx(struct mtk_chan *c)
mtk_uart_apdma_write(c, VFF_RPT, 0);
mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B);
- if (mtkd->support_33bits)
- mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B);
+ if (mtkd->support_bits > VFF_ORI_ADDR_BITS_NUM)
+ mtk_uart_apdma_write(c, VFF_4G_SUPPORT,
+ upper_32_bits(d->addr));
}
mtk_uart_apdma_write(c, VFF_INT_EN, VFF_RX_INT_EN_B);
@@ -296,7 +301,7 @@ static int mtk_uart_apdma_alloc_chan_resources(struct dma_chan *chan)
return -EINVAL;
}
- if (mtkd->support_33bits)
+ if (mtkd->support_bits > VFF_ORI_ADDR_BITS_NUM)
mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_CLR_B);
return ret;
@@ -465,8 +470,14 @@ static void mtk_uart_apdma_free(struct mtk_uart_apdmadev *mtkd)
}
}
+static const struct mtk_uart_apdmacomp mt6779_comp = {
+ .addr_bits = 34
+};
+
static const struct of_device_id mtk_uart_apdma_match[] = {
- { .compatible = "mediatek,mt6577-uart-dma", },
+ { .compatible = "mediatek,mt6577-uart-dma", .data = NULL},
+ { .compatible = "mediatek,mt2712-uart-dma", .data = NULL},
+ { .compatible = "mediatek,mt6779-uart-dma", .data = &mt6779_comp},
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, mtk_uart_apdma_match);
@@ -475,9 +486,10 @@ static int mtk_uart_apdma_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct mtk_uart_apdmadev *mtkd;
- int bit_mask = 32, rc;
+ int rc;
struct mtk_chan *c;
unsigned int i;
+ const struct mtk_uart_apdmacomp *comp;
mtkd = devm_kzalloc(&pdev->dev, sizeof(*mtkd), GFP_KERNEL);
if (!mtkd)
@@ -490,13 +502,26 @@ static int mtk_uart_apdma_probe(struct platform_device *pdev)
return rc;
}
- if (of_property_read_bool(np, "mediatek,dma-33bits"))
- mtkd->support_33bits = true;
+ comp = of_device_get_match_data(&pdev->dev);
+ if (!comp) {
+ /*In order to compatiable with legacy device tree file*/
+ dev_info(&pdev->dev,
+ "No compatiable, using DTS configuration\n");
+
+ if (of_property_read_bool(pdev->dev.of_node,
+ "mediatek,dma-33bits")) {
+ mtkd->support_bits = 33;
+ }
+
+ } else {
+ mtkd->support_bits = comp->addr_bits;
+ }
- if (mtkd->support_33bits)
- bit_mask = 33;
+ dev_info(&pdev->dev,
+ "DMA address bits: %d\n", mtkd->support_bits);
- rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(bit_mask));
+ rc = dma_set_mask_and_coherent(&pdev->dev,
+ DMA_BIT_MASK(mtkd->support_bits));
if (rc)
return rc;
--
2.18.0
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