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Message-Id: <1594992579-20662-1-git-send-email-akhilpo@codeaurora.org>
Date: Fri, 17 Jul 2020 18:59:33 +0530
From: Akhil P Oommen <akhilpo@...eaurora.org>
To: freedreno@...ts.freedesktop.org
Cc: dri-devel@...edesktop.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, jcrouse@...eaurora.org,
smasetty@...eaurora.org, devicetree@...r.kernel.org,
mka@...omium.org, saravanak@...gle.com, sibis@...eaurora.org,
viresh.kumar@...aro.org, jonathan@...ek.ca, robdclark@...il.com,
bjorn.andersson@...aro.org
Subject: [PATCH v6 0/6] Add support for GPU DDR BW scaling
This series add support for GPU DDR bandwidth scaling and is based on the
bindings from Georgi [1]. This is mostly a rebase of Sharat's patches [2] on the
tip of msm-next branch.
[1] https://kernel.googlesource.com/pub/scm/linux/kernel/git/vireshk/pm/+log/opp/linux-next/
[2] https://patchwork.freedesktop.org/series/75291/
Changes from v5:
- Added "interconnect-names" property
Changes from v4:
- Squashed a patch to another one to fix Jonathan's comment
- Add back the pm_runtime_get_if_in_use() check
Changes from v3:
- Rebased on top of Jonathan's patch which adds support for changing gpu freq
through hfi on newer targets
- As suggested by Rob, left the icc_path intact for pre-a6xx GPUs
Sharat Masetty (6):
dt-bindings: drm/msm/gpu: Document gpu opp table
drm: msm: a6xx: send opp instead of a frequency
drm: msm: a6xx: use dev_pm_opp_set_bw to scale DDR
arm64: dts: qcom: SDM845: Enable GPU DDR bw scaling
arm64: dts: qcom: sc7180: Add interconnects property for GPU
arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU opp
.../devicetree/bindings/display/msm/gpu.txt | 28 ++++++
arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 108 ++++++++++++---------
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +-
drivers/gpu/drm/msm/msm_gpu.c | 3 +-
drivers/gpu/drm/msm/msm_gpu.h | 3 +-
7 files changed, 114 insertions(+), 50 deletions(-)
--
2.7.4
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