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Message-Id: <20200717140554.22863-12-kan.liang@linux.intel.com>
Date: Fri, 17 Jul 2020 07:05:51 -0700
From: kan.liang@...ux.intel.com
To: peterz@...radead.org, acme@...hat.com, mingo@...nel.org,
linux-kernel@...r.kernel.org
Cc: jolsa@...nel.org, eranian@...gle.com,
alexander.shishkin@...ux.intel.com, ak@...ux.intel.com,
Kan Liang <kan.liang@...ux.intel.com>
Subject: [PATCH V6 11/14] perf/x86/intel: Disable sample-read the slots and metrics events
From: Kan Liang <kan.liang@...ux.intel.com>
Users fail to sample-read the slots and metrics events, e.g.,
perf record -e '{slots, topdown-retiring}:S'.
When reading the metrics event, the fixed counter 3 (slots) has to be
reset, which impacts the sampling of the slots event.
Add a specific validate_group() support to reject the case and error out
for Ice Lake.
An alternative fix may unconditionally disable slots sampling, but it's
not a decent fix. Users may want to only sample the slot events
without the topdown metrics events.
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
---
arch/x86/events/core.c | 4 ++++
arch/x86/events/intel/core.c | 20 ++++++++++++++++++++
arch/x86/events/perf_event.h | 2 ++
3 files changed, 26 insertions(+)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index c25dde095bca..7a4c26b89cbf 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2176,7 +2176,11 @@ static int validate_group(struct perf_event *event)
fake_cpuc->n_events = 0;
ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
+ if (ret)
+ goto out;
+ if (x86_pmu.validate_group)
+ ret = x86_pmu.validate_group(fake_cpuc, n);
out:
free_fake_cpuc(fake_cpuc);
return ret;
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index dd3d9f3f2162..bcd96d7fb6ec 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4576,6 +4576,25 @@ static __init void intel_ht_bug(void)
x86_pmu.stop_scheduling = intel_stop_scheduling;
}
+static int icl_validate_group(struct cpu_hw_events *cpuc, int n)
+{
+ bool has_sampling_slots = false, has_metrics = false;
+ struct perf_event *e;
+ int i;
+
+ for (i = 0; i < n; i++) {
+ e = cpuc->event_list[i];
+ if (is_slots_event(e) && is_sampling_event(e))
+ has_sampling_slots = true;
+
+ if (is_metric_event(e))
+ has_metrics = true;
+ }
+ if (unlikely(has_sampling_slots && has_metrics))
+ return -EINVAL;
+ return 0;
+}
+
EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
@@ -5437,6 +5456,7 @@ __init int intel_pmu_init(void)
intel_pmu_pebs_data_source_skl(pmem);
x86_pmu.update_topdown_event = icl_update_topdown_event;
x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
+ x86_pmu.validate_group = icl_validate_group;
pr_cont("Icelake events, ");
name = "icelake";
break;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 8100c21205e8..acd85baeabd8 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -677,6 +677,8 @@ struct x86_pmu {
int perfctr_second_write;
u64 (*limit_period)(struct perf_event *event, u64 l);
+ int (*validate_group)(struct cpu_hw_events *cpuc, int n);
+
/* PMI handler bits */
unsigned int late_ack :1,
enabled_ack :1,
--
2.17.1
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