linux-kernel - Re: [PATCH] ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema

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Date:   Tue, 21 Jul 2020 10:43:59 +0800
From:   Wei Xu <xuwei5@...ilicon.com>
To:     Krzysztof Kozlowski <krzk@...nel.org>,
        <linux-kernel@...r.kernel.org>
CC:     Rob Herring <robh+dt@...nel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>
Subject: Re: [PATCH] ARM: dts: hisilicon: Align L2 cache-controller nodename
 with dtschema

Hi Krzysztof,

On 2020/6/26 16:06, Krzysztof Kozlowski wrote:
> Fix dtschema validator warnings like:
>     l2-cache: $nodename:0: 'l2-cache' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@...nel.org>

Thanks!
Applied to the hisilicon arm32 dt tree.

Best Regards,
Wei

> ---
>  arch/arm/boot/dts/hi3620.dtsi     | 2 +-
>  arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
> index 9c207a690df5..f0af1bf2b4d8 100644
> --- a/arch/arm/boot/dts/hi3620.dtsi
> +++ b/arch/arm/boot/dts/hi3620.dtsi
> @@ -71,7 +71,7 @@
>  		interrupt-parent = <&gic>;
>  		ranges = <0 0xfc000000 0x2000000>;
>  
> -		L2: l2-cache {
> +		L2: cache-controller {
>  			compatible = "arm,pl310-cache";
>  			reg = <0x100000 0x100000>;
>  			interrupts = <0 15 4>;
> diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
> index 696e6982a688..3ee7967c202d 100644
> --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
> +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
> @@ -381,7 +381,7 @@
>  			interrupts = <1 13 0xf01>;
>  		};
>  
> -		l2: l2-cache {
> +		l2: cache-controller {
>  			compatible = "arm,pl310-cache";
>  			reg = <0x00a10000 0x100000>;
>  			interrupts = <0 15 4>;
>