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Date: Tue, 21 Jul 2020 17:08:07 +0530 From: Srikar Dronamraju <srikar@...ux.vnet.ibm.com> To: Michael Ellerman <michaele@....ibm.com> Cc: Srikar Dronamraju <srikar@...ux.vnet.ibm.com>, linuxppc-dev <linuxppc-dev@...ts.ozlabs.org>, LKML <linux-kernel@...r.kernel.org>, Ingo Molnar <mingo@...nel.org>, Peter Zijlstra <peterz@...radead.org>, Valentin Schneider <valentin.schneider@....com>, Nick Piggin <npiggin@....ibm.com>, Oliver OHalloran <oliveroh@....ibm.com>, Nathan Lynch <nathanl@...ux.ibm.com>, Michael Neuling <mikey@...ux.ibm.com>, Anton Blanchard <anton@....ibm.com>, Gautham R Shenoy <ego@...ux.vnet.ibm.com>, Vaidyanathan Srinivasan <svaidy@...ux.ibm.com>, Jordan Niethe <jniethe5@...il.com> Subject: [PATCH v2 03/10] powerpc/smp: Move powerpc_topology above Just moving the powerpc_topology description above. This will help in using functions in this file and avoid declarations. No other functional changes Cc: linuxppc-dev <linuxppc-dev@...ts.ozlabs.org> Cc: LKML <linux-kernel@...r.kernel.org> Cc: Michael Ellerman <michaele@....ibm.com> Cc: Ingo Molnar <mingo@...nel.org> Cc: Peter Zijlstra <peterz@...radead.org> Cc: Valentin Schneider <valentin.schneider@....com> Cc: Nick Piggin <npiggin@....ibm.com> Cc: Oliver OHalloran <oliveroh@....ibm.com> Cc: Nathan Lynch <nathanl@...ux.ibm.com> Cc: Michael Neuling <mikey@...ux.ibm.com> Cc: Anton Blanchard <anton@....ibm.com> Cc: Gautham R Shenoy <ego@...ux.vnet.ibm.com> Cc: Vaidyanathan Srinivasan <svaidy@...ux.ibm.com> Cc: Jordan Niethe <jniethe5@...il.com> Reviewed-by: Gautham R. Shenoy <ego@...ux.vnet.ibm.com> Signed-off-by: Srikar Dronamraju <srikar@...ux.vnet.ibm.com> --- arch/powerpc/kernel/smp.c | 116 +++++++++++++++++++------------------- 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 0e0b118d9b6e..1ce95da00cb6 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -818,6 +818,64 @@ static int init_cpu_l1_cache_map(int cpu) return err; } +static bool shared_caches; + +#ifdef CONFIG_SCHED_SMT +/* cpumask of CPUs with asymmetric SMT dependency */ +static int powerpc_smt_flags(void) +{ + int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; + + if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { + printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); + flags |= SD_ASYM_PACKING; + } + return flags; +} +#endif + +/* + * P9 has a slightly odd architecture where pairs of cores share an L2 cache. + * This topology makes it *much* cheaper to migrate tasks between adjacent cores + * since the migrated task remains cache hot. We want to take advantage of this + * at the scheduler level so an extra topology level is required. + */ +static int powerpc_shared_cache_flags(void) +{ + return SD_SHARE_PKG_RESOURCES; +} + +/* + * We can't just pass cpu_l2_cache_mask() directly because + * returns a non-const pointer and the compiler barfs on that. + */ +static const struct cpumask *shared_cache_mask(int cpu) +{ + if (shared_caches) + return cpu_l2_cache_mask(cpu); + + if (has_big_cores) + return cpu_smallcore_mask(cpu); + + return per_cpu(cpu_sibling_map, cpu); +} + +#ifdef CONFIG_SCHED_SMT +static const struct cpumask *smallcore_smt_mask(int cpu) +{ + return cpu_smallcore_mask(cpu); +} +#endif + +static struct sched_domain_topology_level powerpc_topology[] = { +#ifdef CONFIG_SCHED_SMT + { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, +#endif + { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) }, + { cpu_cpu_mask, SD_INIT_NAME(DIE) }, + { NULL, }, +}; + static int init_big_cores(void) { int cpu; @@ -1249,8 +1307,6 @@ static void add_cpu_to_masks(int cpu) set_cpus_related(cpu, i, cpu_core_mask); } -static bool shared_caches; - /* Activate a secondary processor. */ void start_secondary(void *unused) { @@ -1314,62 +1370,6 @@ int setup_profiling_timer(unsigned int multiplier) return 0; } -#ifdef CONFIG_SCHED_SMT -/* cpumask of CPUs with asymmetric SMT dependency */ -static int powerpc_smt_flags(void) -{ - int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; - - if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { - printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); - flags |= SD_ASYM_PACKING; - } - return flags; -} -#endif - -/* - * P9 has a slightly odd architecture where pairs of cores share an L2 cache. - * This topology makes it *much* cheaper to migrate tasks between adjacent cores - * since the migrated task remains cache hot. We want to take advantage of this - * at the scheduler level so an extra topology level is required. - */ -static int powerpc_shared_cache_flags(void) -{ - return SD_SHARE_PKG_RESOURCES; -} - -/* - * We can't just pass cpu_l2_cache_mask() directly because - * returns a non-const pointer and the compiler barfs on that. - */ -static const struct cpumask *shared_cache_mask(int cpu) -{ - if (shared_caches) - return cpu_l2_cache_mask(cpu); - - if (has_big_cores) - return cpu_smallcore_mask(cpu); - - return per_cpu(cpu_sibling_map, cpu); -} - -#ifdef CONFIG_SCHED_SMT -static const struct cpumask *smallcore_smt_mask(int cpu) -{ - return cpu_smallcore_mask(cpu); -} -#endif - -static struct sched_domain_topology_level powerpc_topology[] = { -#ifdef CONFIG_SCHED_SMT - { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, -#endif - { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) }, - { cpu_cpu_mask, SD_INIT_NAME(DIE) }, - { NULL, }, -}; - void __init smp_cpus_done(unsigned int max_cpus) { /* -- 2.17.1
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