linux-kernel - Re: nouveau regression with 5.7 caused by "PCI/PM: Assume ports without DLL Link Active train links in 100 ms"

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20200721130847.GK5180@lahna.fi.intel.com>
Date:   Tue, 21 Jul 2020 16:08:47 +0300
From:   Mika Westerberg <mika.westerberg@...ux.intel.com>
To:     Lukas Wunner <lukas@...ner.de>
Cc:     Lyude Paul <lyude@...hat.com>, Bjorn Helgaas <helgaas@...nel.org>,
        Karol Herbst <kherbst@...hat.com>,
        Sasha Levin <sashal@...nel.org>,
        Patrick Volkerding <volkerdi@...il.com>,
        Linux PCI <linux-pci@...r.kernel.org>,
        linux-kernel@...r.kernel.org,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        Kai-Heng Feng <kai.heng.feng@...onical.com>,
        Ben Skeggs <bskeggs@...hat.com>,
        nouveau <nouveau@...ts.freedesktop.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: nouveau regression with 5.7 caused by "PCI/PM: Assume ports
 without DLL Link Active train links in 100 ms"

On Fri, Jul 17, 2020 at 09:52:09PM +0200, Lukas Wunner wrote:
> On Fri, Jul 17, 2020 at 03:04:10PM -0400, Lyude Paul wrote:
> > Isn't it possible to tell whether a PCI device is connected through
> > thunderbolt or not? We could probably get away with just defaulting
> > to 100ms for thunderbolt devices without DLL Link Active specified,
> > and then default to the old delay value for non-thunderbolt devices.
> 
> pci_is_thunderbolt_attached()

That only works with some devices. I think we should try to keep the
fact that some PCIe links may be tunneled over TBT/USB4 transparent to
the PCI core and try to treat them as "standard" PCIe links if possible
at all :)