lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Tue, 21 Jul 2020 09:01:13 -0600 From: Mathieu Poirier <mathieu.poirier@...aro.org> To: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org> Cc: Andy Gross <agross@...nel.org>, Bjorn Andersson <bjorn.andersson@...aro.org>, Suzuki K Poulose <suzuki.poulose@....com>, Mike Leach <mike.leach@...aro.org>, devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH] arm64: dts: qcom: sdm845: Support ETMv4 power management On Tue, Jul 21, 2020 at 12:43:43PM +0530, Sai Prakash Ranjan wrote: > Add "arm,coresight-loses-context-with-cpu" property to coresight > ETM nodes to avoid failure of trace session because of losing > context on entering deep idle states. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org> > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) Reviewed-by: Mathieu Poirier <mathieu.poirier@...aro.org> > > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index e506793407d8..0b5f063dcaea 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -3016,6 +3016,7 @@ etm@...0000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3035,6 +3036,7 @@ etm@...0000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3054,6 +3056,7 @@ etm@...0000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3073,6 +3076,7 @@ etm@...0000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3092,6 +3096,7 @@ etm@...0000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3111,6 +3116,7 @@ etm@...0000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3130,6 +3136,7 @@ etm@...0000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > @@ -3149,6 +3156,7 @@ etm@...0000 { > > clocks = <&aoss_qmp>; > clock-names = "apb_pclk"; > + arm,coresight-loses-context-with-cpu; > > out-ports { > port { > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >
Powered by blists - more mailing lists