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Date: Wed, 22 Jul 2020 16:51:59 +0800 From: Nicolas Boichat <drinkcat@...omium.org> To: Weiyi Lu <weiyi.lu@...iatek.com> Cc: Matthias Brugger <matthias.bgg@...il.com>, Rob Herring <robh@...nel.org>, Stephen Boyd <sboyd@...nel.org>, James Liao <jamesjj.liao@...iatek.com>, linux-arm Mailing List <linux-arm-kernel@...ts.infradead.org>, lkml <linux-kernel@...r.kernel.org>, "moderated list:ARM/Mediatek SoC support" <linux-mediatek@...ts.infradead.org>, linux-clk@...r.kernel.org, srv_heupstream <srv_heupstream@...iatek.com>, Wendell Lin <wendell.lin@...iatek.com>, Ikjoon Jang <ikjn@...omium.org> Subject: Re: [PATCH 3/4] clk: mediatek: Add configurable enable control to mtk_pll_data On Wed, Jul 22, 2020 at 2:50 PM Weiyi Lu <weiyi.lu@...iatek.com> wrote: > > In all MediaTek PLL design, bit 0 of CON0 register is always > the enable bit. > However, there's a special case of usbpll on MT8192. > The enable bit of usbpll is moved to bit 2 of other register. > Add configurable en_reg and base_en_bit for enable control or > using the default if without setting in pll data. > > Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com> > --- > drivers/clk/mediatek/clk-mtk.h | 2 ++ > drivers/clk/mediatek/clk-pll.c | 26 ++++++++++++++++++++++---- > 2 files changed, 24 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h > index c3d6756..8bb0b3d 100644 > --- a/drivers/clk/mediatek/clk-mtk.h > +++ b/drivers/clk/mediatek/clk-mtk.h > @@ -233,6 +233,8 @@ struct mtk_pll_data { > uint32_t pcw_chg_reg; > const struct mtk_pll_div_table *div_table; > const char *parent_name; > + uint32_t en_reg; > + uint8_t base_en_bit; > }; > > void mtk_clk_register_plls(struct device_node *node, > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index f440f2cd..b8ccd42 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -44,6 +44,7 @@ struct mtk_clk_pll { > void __iomem *tuner_en_addr; > void __iomem *pcw_addr; > void __iomem *pcw_chg_addr; > + void __iomem *en_addr; > const struct mtk_pll_data *data; > }; > > @@ -56,7 +57,10 @@ static int mtk_pll_is_prepared(struct clk_hw *hw) > { > struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); > > - return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; > + if (pll->en_addr) > + return (readl(pll->en_addr) & BIT(pll->data->base_en_bit)) != 0; > + else > + return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; > } > > static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, > @@ -251,6 +255,12 @@ static int mtk_pll_prepare(struct clk_hw *hw) > r |= pll->data->en_mask; > writel(r, pll->base_addr + REG_CON0); > This is not a new change, but I'm wondering if the asymmetry is intentional here, that is, prepare sets bit pll->data->en_mask of REG_CON0; unprepare clears CON0_BASE_EN of REG_CON0. With this patch, if pll->en_addr is set, you set both pll->data->en_mask _and_ pll->data->base_en_bit, and clear only pll->data->base_en_bit. > + if (pll->en_addr) { > + r = readl(pll->en_addr); > + r |= BIT(pll->data->base_en_bit); > + writel(r, pll->en_addr); > + } > + > __mtk_pll_tuner_enable(pll); > > udelay(20); > @@ -277,9 +287,15 @@ static void mtk_pll_unprepare(struct clk_hw *hw) > > __mtk_pll_tuner_disable(pll); > > - r = readl(pll->base_addr + REG_CON0); > - r &= ~CON0_BASE_EN; > - writel(r, pll->base_addr + REG_CON0); > + if (pll->en_addr) { > + r = readl(pll->en_addr); > + r &= ~BIT(pll->data->base_en_bit); > + writel(r, pll->en_addr); > + } else { > + r = readl(pll->base_addr + REG_CON0); > + r &= ~CON0_BASE_EN; > + writel(r, pll->base_addr + REG_CON0); > + } > > r = readl(pll->pwr_addr) | CON0_ISO_EN; > writel(r, pll->pwr_addr); > @@ -321,6 +337,8 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, > pll->tuner_addr = base + data->tuner_reg; > if (data->tuner_en_reg) > pll->tuner_en_addr = base + data->tuner_en_reg; > + if (data->en_reg) > + pll->en_addr = base + data->en_reg; If the answer to my question above holds (asymmetry is not intentional), this patch/the code could be simplified a lot if you also added a pll->en_bit member, and, here, did this: if (pll->en_reg) { pll->en_addr = base + data->en_reg; pll->end_bit = data->en_bit; } else { pll->en_addr = pll->base_addr + REG_CON0; pll->en_bit = CON0_BASE_EN; } > pll->hw.init = &init; > pll->data = data; > > -- > 1.8.1.1.dirty
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