linux-kernel - Re: [PATCH 1/2] Revert "i2c: cadence: Fix the hold bit setting"

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Message-ID: <20200722102859.GI1030@ninjato>
Date:   Wed, 22 Jul 2020 12:29:00 +0200
From:   Wolfram Sang <wsa@...nel.org>
To:     Raviteja Narayanam <raviteja.narayanam@...inx.com>
Cc:     linux-i2c@...r.kernel.org, michal.simek@...inx.com,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        git@...inx.com
Subject: Re: [PATCH 1/2] Revert "i2c: cadence: Fix the hold bit setting"

On Fri, Jul 03, 2020 at 07:25:49PM +0530, Raviteja Narayanam wrote:
> This reverts commit d358def706880defa4c9e87381c5bf086a97d5f9.
> 
> There are two issues with "i2c: cadence: Fix the hold bit setting" commit.
> 
> 1. In case of combined message request from user space, when the HOLD
> bit is cleared in cdns_i2c_mrecv function, a STOP condition is sent
> on the bus even before the last message is started. This is because when
> the HOLD bit is cleared, the FIFOS are empty and there is no pending
> transfer. The STOP condition should occur only after the last message
> is completed.
> 
> 2. The code added by the commit is redundant. Driver is handling the
> setting/clearing of HOLD bit in right way before the commit.
> 
> The setting of HOLD bit based on 'bus_hold_flag' is taken care in
> cdns_i2c_master_xfer function even before cdns_i2c_msend/cdns_i2c_recv
> functions.
> 
> The clearing of HOLD bit is taken care at the end of cdns_i2c_msend and
> cdns_i2c_recv functions based on bus_hold_flag and byte count.
> Since clearing of HOLD bit is done after the slave address is written to
> the register (writing to address register triggers the message transfer),
> it is ensured that STOP condition occurs at the right time after
> completion of the pending transfer (last message).
> 
> Signed-off-by: Raviteja Narayanam <raviteja.narayanam@...inx.com>

Applied to for-current, thanks!


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