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Message-ID: <d6cf82bd-70ad-19e9-36ef-35c9db92fa56@linaro.org>
Date:   Thu, 23 Jul 2020 16:34:07 +0200
From:   Daniel Lezcano <daniel.lezcano@...aro.org>
To:     Anup Patel <anup.patel@....com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Rob Herring <robh+dt@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>
Cc:     Damien Le Moal <damien.lemoal@....com>,
        Atish Patra <atish.patra@....com>,
        Alistair Francis <Alistair.Francis@....com>,
        Anup Patel <anup@...infault.org>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, Emil Renner Berhing <kernel@...il.dk>
Subject: Re: [PATCH v5 2/4] clocksource/drivers: Add CLINT timer driver

On 23/07/2020 16:24, Anup Patel wrote:
> We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e.
> RISC-V NoMMU kernel).
> 
> The CLINT MMIO device provides three things:
> 1. 64bit free running counter register
> 2. 64bit per-CPU time compare registers
> 3. 32bit per-CPU inter-processor interrupt registers
> 
> Unlike other timer devices, CLINT provides IPI registers along with
> timer registers. To use CLINT IPI registers, the CLINT timer driver
> provides IPI related callbacks to arch/riscv.
> 
> Signed-off-by: Anup Patel <anup.patel@....com>
> Tested-by: Emil Renner Berhing <kernel@...il.dk>
> ---

Acked-by: Daniel Lezcano <daniel.lezcano@...aro.org>



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