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Date:   Fri, 24 Jul 2020 17:16:05 +0800
From:   Wei Li <liwei391@...wei.com>
To:     Adrian Hunter <adrian.hunter@...el.com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        James Clark <james.clark@....com>,
        Jiri Olsa <jolsa@...hat.com>, Leo Yan <leo.yan@...aro.org>,
        Mark Rutland <mark.rutland@....com>,
        Namhyung Kim <namhyung@...nel.org>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Will Deacon <will@...nel.org>, <zhangshaokun@...ilicon.com>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, Ingo Molnar <mingo@...hat.com>,
        Peter Zijlstra <peterz@...radead.org>, <guohanjun@...wei.com>
Subject: [PATCH 2/4] perf: arm-spe: Add support for ARMv8.3-SPE

Armv8.3 extends the SPE by adding:
- Alignment field in the Events packet, and filtering on this event
  using PMSEVFR_EL1.
- Support for the Scalable Vector Extension (SVE).

The main additions for SVE are:
- Recording the vector length for SVE operations in the Operation Type
  packet. It is not possible to filter on vector length.
- Incomplete predicate and empty predicate fields in the Events packet,
  and filtering on these events using PMSEVFR_EL1.

Add the corresponding decode process of Events packet and Operation Type
packet in perf tool.

Signed-off-by: Wei Li <liwei391@...wei.com>
---
 .../arm-spe-decoder/arm-spe-pkt-decoder.c     | 69 ++++++++++++++++++-
 1 file changed, 67 insertions(+), 2 deletions(-)

diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
index b94001b756c7..10a3692839de 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
@@ -347,6 +347,24 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
 				blen -= ret;
 			}
 		}
+		if (idx > 2) {
+			if (payload & 0x800) {
+				ret = snprintf(buf, buf_len, " ALIGNMENT");
+				buf += ret;
+				blen -= ret;
+			}
+			if (payload & 0x20000) {
+				ret = snprintf(buf, buf_len, " SVE-PRED-PARTIAL");
+				buf += ret;
+				blen -= ret;
+			}
+			if (payload & 0x40000) {
+				ret = snprintf(buf, buf_len, " SVE-PRED-EMPTY");
+				buf += ret;
+				blen -= ret;
+			}
+		}
+
 		if (ret < 0)
 			return ret;
 		blen -= ret;
@@ -354,8 +372,38 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
 	}
 	case ARM_SPE_OP_TYPE:
 		switch (idx) {
-		case 0:	return snprintf(buf, buf_len, "%s", payload & 0x1 ?
-					"COND-SELECT" : "INSN-OTHER");
+		case 0:	{
+			if (payload & 0x8) {
+				size_t blen = buf_len;
+
+				ret = snprintf(buf, buf_len, "SVE-OTHER");
+				buf += ret;
+				blen -= ret;
+				if (payload & 0x2) {
+					ret = snprintf(buf, buf_len, " FP");
+					buf += ret;
+					blen -= ret;
+				}
+				if (payload & 0x4) {
+					ret = snprintf(buf, buf_len, " PRED");
+					buf += ret;
+					blen -= ret;
+				}
+				if (payload & 0x70) {
+					ret = snprintf(buf, buf_len, " EVL %d",
+						32 << ((payload & 0x70) >> 4));
+					buf += ret;
+					blen -= ret;
+				}
+				if (ret < 0)
+					return ret;
+				blen -= ret;
+				return buf_len - blen;
+			} else {
+				return snprintf(buf, buf_len, "%s", payload & 0x1 ?
+						"COND-SELECT" : "INSN-OTHER");
+			}
+		}
 		case 1:	{
 			size_t blen = buf_len;
 
@@ -385,6 +433,23 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf,
 				ret = snprintf(buf, buf_len, " SIMD-FP");
 				buf += ret;
 				blen -= ret;
+			} else if (payload & 0x8) {
+				if (payload & 0x4) {
+					ret = snprintf(buf, buf_len, " PRED");
+					buf += ret;
+					blen -= ret;
+				}
+				if (payload & 0x70) {
+					ret = snprintf(buf, buf_len, " EVL %d",
+						32 << ((payload & 0x70) >> 4));
+					buf += ret;
+					blen -= ret;
+				}
+				if (payload & 0x80) {
+					ret = snprintf(buf, buf_len, " SG");
+					buf += ret;
+					blen -= ret;
+				}
 			}
 			if (ret < 0)
 				return ret;
-- 
2.17.1

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