linux-kernel - Re: [PATCH v2 16/18] clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs

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Message-ID: <159558252415.3847286.3699918620483470980@swboyd.mtv.corp.google.com>
Date:   Fri, 24 Jul 2020 02:22:04 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Claudiu Beznea <claudiu.beznea@...rochip.com>,
        alexandre.belloni@...tlin.com, ludovic.desroches@...rochip.com,
        mturquette@...libre.com, nicolas.ferre@...rochip.com
Cc:     bbrezillon@...nel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Claudiu Beznea <claudiu.beznea@...rochip.com>
Subject: Re: [PATCH v2 16/18] clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs

Quoting Claudiu Beznea (2020-07-22 00:38:24)
> Some of the SAMA7G5 PLLs support multiple outputs (e.g. AUDIO PLL).
> For these, split the PLL clock in two: fractional clock and
> divider clock. In case PLLs supports multiple outputs (since these
> outputs are dividers (with different settings) sharing the same
> fractional part), it will register one fractional clock and multiple
> divider clocks (dividers sharing the fractional clock).
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
> ---

Applied to clk-next