linux-kernel - Re: [PATCH 0/4] x86/cpu: Use SERIALIZE in sync

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20200727110708.GA3174@gmail.com>
Date:   Mon, 27 Jul 2020 13:07:08 +0200
From:   Ingo Molnar <mingo@...nel.org>
To:     Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>, Borislav Petkov <bp@...e.de>,
        Andy Lutomirski <luto@...nel.org>, x86@...nel.org,
        Dave Hansen <dave.hansen@...el.com>,
        Tony Luck <tony.luck@...el.com>,
        Cathy Zhang <cathy.zhang@...el.com>,
        Fenghua Yu <fenghua.yu@...el.com>,
        "H. Peter Anvin" <hpa@...or.com>,
        Kyung Min Park <kyung.min.park@...el.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>,
        "Ravi V. Shankar" <ravi.v.shankar@...el.com>,
        Sean Christopherson <sean.j.christopherson@...el.com>,
        linux-kernel@...r.kernel.org, Ricardo Neri <ricardo.neri@...el.com>
Subject: Re: [PATCH 0/4] x86/cpu: Use SERIALIZE in sync_core()


* Ricardo Neri <ricardo.neri-calderon@...ux.intel.com> wrote:

> A recent submission to LKML introduced a CPU feature flag for a new
> Intel architecture Serializing Instruction, SERIALIZE [1]. Unlike the
> existing Serializing Instructions, this new instruction does not have
> side effects such as clobbering registers or exiting to a hypervisor.
> 
> As stated in the Intel "extensions" (ISE) manual [2], this instruction
> will appear first in Sapphire Rapids and Alder Lake.
> 
> Andy Lutomirski suggested to use this instruction in sync_core() as it
> serves the very purpose of this function [3].
> 
> For completeness, I picked patch #3 from Cathy's series (and has become
> patch #1 here) [1]. Her series depends on such patch to build correctly.
> Maybe it can be merged independently while the discussion continues?
> 
> Thanks and BR,
> Ricardo
> 
> [1]. https://lore.kernel.org/kvm/1594088183-7187-1-git-send-email-cathy.zhang@intel.com/
> [2]. https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
> [3]. https://lore.kernel.org/kvm/CALCETrWudiF8G8r57r5i4JefuP5biG1kHg==0O8YXb-bYS-0BA@mail.gmail.com/
> 
> Ricardo Neri (4):
>   x86/cpufeatures: Add enumeration for SERIALIZE instruction
>   x86/cpu: Relocate sync_core() to sync_core.h
>   x86/cpu: Refactor sync_core() for readability
>   x86/cpu: Use SERIALIZE in sync_core() when available

I've picked up the first 3 preparatory patches into tip:x86/cpu, as 
they are valid improvements even without the 4th patch. The actual 
functionality in the 4th patch still needs work.

Thannks,

	Ingo