linux-kernel - [PATCH v4 0/5] Add TI PRUSS Local Interrupt Controller IRQChip driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <1595927918-19845-1-git-send-email-grzegorz.jaszczyk@linaro.org>
Date:   Tue, 28 Jul 2020 11:18:33 +0200
From:   Grzegorz Jaszczyk <grzegorz.jaszczyk@...aro.org>
To:     tglx@...utronix.de, jason@...edaemon.net, maz@...nel.org,
        s-anna@...com
Cc:     grzegorz.jaszczyk@...aro.org, robh+dt@...nel.org,
        lee.jones@...aro.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-omap@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, david@...hnology.com,
        wmills@...com, praneeth@...com
Subject: [PATCH v4 0/5] Add TI PRUSS Local Interrupt Controller IRQChip driver

Hi All,

The following is a v4 version of the series [1][2][3] that adds an IRQChip
driver for the local interrupt controller present within a Programmable
Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) present on a
number of TI SoCs including OMAP architecture based AM335x, AM437x, AM57xx SoCs,
Keystone 2 architecture based 66AK2G SoCs, Davinci architecture based
OMAP-L138/DA850 SoCs and the latest K3 architecture based AM65x and J721E SoCs.
Please see the v1 cover-letter [1] for details about the features of this
interrupt controller.  More details can be found in any of the supported SoC
TRMs.  Eg: Chapter 30.1.6 of AM5728 TRM [4]

Please see the individual patches for exact changes in each patch, following are
the main changes from v3:
 - Change interrupt-cells to 3 in order to provide 2-level mapping description
   in DT for interrupts routed to the main CPU as Marc requested (patch #1 and
   patch #2).
 - Get rid of the two distinct code paths in the xlate function and allow to
   proceed only with 3 parameters description as Marc suggested (patch #2).
 - Due to above modification squash patch #6 of previous patchset into patch #2.
 - Merge the irqs-reserved and irqs-shared to one property (patch #1 and #2).

[1] https://patchwork.kernel.org/cover/11034561/
[2] https://patchwork.kernel.org/cover/11069749/
[3] https://patchwork.kernel.org/cover/11639055/
[4] http://www.ti.com/lit/pdf/spruhz6

Best regards
Grzegorz

David Lechner (1):
  irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops

Grzegorz Jaszczyk (1):
  irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS
    interrupts

Suman Anna (3):
  dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings
  irqchip/irq-pruss-intc: Add logic for handling reserved interrupts
  irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs

 .../interrupt-controller/ti,pruss-intc.yaml        | 157 +++++
 drivers/irqchip/Kconfig                            |  10 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-pruss-intc.c                   | 659 +++++++++++++++++++++
 4 files changed, 827 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
 create mode 100644 drivers/irqchip/irq-pruss-intc.c

-- 
2.7.4