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Message-ID: <1596012277-8448-1-git-send-email-weiyi.lu@mediatek.com>
Date: Wed, 29 Jul 2020 16:44:32 +0800
From: Weiyi Lu <weiyi.lu@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
Nicolas Boichat <drinkcat@...omium.org>
CC: James Liao <jamesjj.liao@...iatek.com>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
<srv_heupstream@...iatek.com>, Weiyi Lu <weiyi.lu@...iatek.com>,
Wendell Lin <wendell.lin@...iatek.com>
Subject: [PATCH v2 0/5] Mediatek MT8192 clock support
This series is based on v5.8-rc1
changes since v1:
- fix asymmetrical control of PLL
- have en_mask used as divider enable mask on all MediaTek SoC
Weiyi Lu (5):
dt-bindings: ARM: Mediatek: Document bindings for MT8192
clk: mediatek: Add dt-bindings for MT8192 clocks
clk: mediatek: Fix asymmetrical PLL enable and disable control
clk: mediatek: Add configurable enable control to mtk_pll_data
clk: mediatek: Add MT8192 clock support
.../arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,audsys.txt | 1 +
.../arm/mediatek/mediatek,camsys-raw.yaml | 40 +
.../bindings/arm/mediatek/mediatek,camsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,imgsys.txt | 2 +
.../arm/mediatek/mediatek,imp_iic_wrap.yaml | 43 +
.../arm/mediatek/mediatek,infracfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,ipesys.txt | 1 +
.../arm/mediatek/mediatek,mdpsys.yaml | 38 +
.../bindings/arm/mediatek/mediatek,mfgcfg.txt | 1 +
.../bindings/arm/mediatek/mediatek,mmsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,msdc.yaml | 39 +
.../arm/mediatek/mediatek,pericfg.yaml | 1 +
.../arm/mediatek/mediatek,scp-adsp.yaml | 38 +
.../arm/mediatek/mediatek,topckgen.txt | 1 +
.../arm/mediatek/mediatek,vdecsys-soc.yaml | 38 +
.../arm/mediatek/mediatek,vdecsys.txt | 1 +
.../arm/mediatek/mediatek,vencsys.txt | 1 +
drivers/clk/mediatek/Kconfig | 146 ++
drivers/clk/mediatek/Makefile | 24 +
drivers/clk/mediatek/clk-mt2701.c | 26 +-
drivers/clk/mediatek/clk-mt2712.c | 30 +-
drivers/clk/mediatek/clk-mt6765.c | 20 +-
drivers/clk/mediatek/clk-mt6779.c | 24 +-
drivers/clk/mediatek/clk-mt6797.c | 20 +-
drivers/clk/mediatek/clk-mt7622.c | 18 +-
drivers/clk/mediatek/clk-mt7629.c | 12 +-
drivers/clk/mediatek/clk-mt8173.c | 42 +-
drivers/clk/mediatek/clk-mt8183.c | 22 +-
drivers/clk/mediatek/clk-mt8192-aud.c | 150 ++
drivers/clk/mediatek/clk-mt8192-cam.c | 69 +
drivers/clk/mediatek/clk-mt8192-cam_rawa.c | 56 +
drivers/clk/mediatek/clk-mt8192-cam_rawb.c | 56 +
drivers/clk/mediatek/clk-mt8192-cam_rawc.c | 56 +
drivers/clk/mediatek/clk-mt8192-img.c | 57 +
drivers/clk/mediatek/clk-mt8192-img2.c | 59 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_c.c | 61 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_e.c | 55 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_n.c | 57 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_s.c | 59 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_w.c | 55 +
.../clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c | 59 +
drivers/clk/mediatek/clk-mt8192-ipe.c | 61 +
drivers/clk/mediatek/clk-mt8192-mdp.c | 89 +
drivers/clk/mediatek/clk-mt8192-mfg.c | 54 +
drivers/clk/mediatek/clk-mt8192-mm.c | 108 ++
drivers/clk/mediatek/clk-mt8192-msdc.c | 54 +
drivers/clk/mediatek/clk-mt8192-msdc_top.c | 83 +
drivers/clk/mediatek/clk-mt8192-scp_adsp.c | 55 +
drivers/clk/mediatek/clk-mt8192-vdec.c | 81 +
drivers/clk/mediatek/clk-mt8192-vdec_soc.c | 86 +
drivers/clk/mediatek/clk-mt8192-venc.c | 57 +
drivers/clk/mediatek/clk-mt8192.c | 1549 +++++++++++++++++
drivers/clk/mediatek/clk-mtk.h | 2 +
drivers/clk/mediatek/clk-mux.h | 15 +
drivers/clk/mediatek/clk-pll.c | 20 +-
include/dt-bindings/clock/mt8192-clk.h | 593 +++++++
57 files changed, 4284 insertions(+), 105 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml
create mode 100644 drivers/clk/mediatek/clk-mt8192-aud.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-cam.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawa.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawb.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawc.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-img.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-img2.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_c.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_n.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_s.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-ipe.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-mdp.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-mfg.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-mm.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc_top.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-scp_adsp.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec_soc.c
create mode 100644 drivers/clk/mediatek/clk-mt8192-venc.c
create mode 100644 drivers/clk/mediatek/clk-mt8192.c
create mode 100644 include/dt-bindings/clock/mt8192-clk.h
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