linux-kernel - [PATCH v1 1/3] arm64: dts: imx8mq: Add NWL MIPI DSI controller

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Message-Id: <41adfe49c75d8bb261dc8d481e9bb537f6699cb4.1596025057.git.agx@sigxcpu.org>
Date:   Wed, 29 Jul 2020 14:19:43 +0200
From:   Guido Günther <agx@...xcpu.org>
To:     Rob Herring <robh+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Martin Kepplinger <martink@...teo.de>,
        "Angus Ainslie (Purism)" <angus@...ea.ca>,
        Guido Günther <agx@...xcpu.org>,
        Anson Huang <Anson.Huang@....com>, Peng Fan <peng.fan@....com>,
        Dong Aisheng <aisheng.dong@....com>,
        Leonard Crestez <leonard.crestez@....com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Lucas Stach <l.stach@...gutronix.de>,
        Andrey Smirnov <andrew.smirnov@...il.com>,
        Li Jun <jun.li@....com>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Li Yang <leoyang.li@....com>, Arnd Bergmann <arnd@...db.de>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Michael Walle <michael@...le.cc>,
        Olof Johansson <olof@...om.net>, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH v1 1/3] arm64: dts: imx8mq: Add NWL MIPI DSI controller

Add a node for the Northwest Logic MIPI DSI IP core, "disabled" by
default. This also adds the necessary port to LCDIF.

Signed-off-by: Guido Günther <agx@...xcpu.org>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 49 +++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index f70435cf9ad5..e5fa77e1dfe7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -523,6 +523,12 @@ lcdif: lcd-controller@...20000 {
 						  <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 				assigned-clock-rates = <0>, <0>, <0>, <594000000>;
 				status = "disabled";
+
+				port@0 {
+					lcdif_mipi_dsi: endpoint {
+						remote-endpoint = <&mipi_dsi_lcdif_in>;
+					};
+				};
 			};
 
 			iomuxc: pinctrl@...30000 {
@@ -899,6 +905,49 @@ sec_jr2: jr@...0 {
 				};
 			};
 
+			mipi_dsi: mipi-dsi@...00000 {
+				compatible = "fsl,imx8mq-nwl-dsi";
+				reg = <0x30a00000 0x300>;
+				clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
+					 <&clk IMX8MQ_CLK_DSI_AHB>,
+					 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
+					 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+					 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
+				clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
+				assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
+						  <&clk IMX8MQ_CLK_DSI_CORE>,
+						  <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
+				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
+							 <&clk IMX8MQ_SYS1_PLL_266M>;
+				assigned-clock-rates = <80000000>, <266000000>, <20000000>;
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+				mux-controls = <&mux 0>;
+				power-domains = <&pgc_mipi>;
+				phys = <&dphy>;
+				phy-names = "dphy";
+				resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
+					 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
+					 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
+					 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
+				reset-names = "byte", "dpi", "esc", "pclk";
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						mipi_dsi_lcdif_in: endpoint@0 {
+							reg = <0>;
+							remote-endpoint = <&lcdif_mipi_dsi>;
+						};
+					};
+				};
+			};
+
 			dphy: dphy@...00300 {
 				compatible = "fsl,imx8mq-mipi-dphy";
 				reg = <0x30a00300 0x100>;
-- 
2.26.2