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Message-ID: <20200729183000.GA30361@xilinx.com>
Date: Wed, 29 Jul 2020 11:30:00 -0700
From: Hyun Kwon <hyun.kwon@...inx.com>
To: Laurent Pinchart <laurent.pinchart@...asonboard.com>
Cc: Wei Yongjun <weiyongjun1@...wei.com>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Michal Simek <michals@...inx.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kernel-janitors@...r.kernel.org" <kernel-janitors@...r.kernel.org>,
Hulk Robot <hulkci@...wei.com>
Subject: Re: [PATCH -next] drm: xlnx: Fix typo in parameter description
Hi Wei,
Thanks for the patch.
On Tue, Jul 28, 2020 at 03:33:49PM -0700, Laurent Pinchart wrote:
> Hi Wei,
>
> Thank you for the patch.
>
> On Sat, Jul 25, 2020 at 06:34:29AM +0000, Wei Yongjun wrote:
> > Fix typo in parameter description.
> >
> > Fixes: d76271d22694 ("drm: xlnx: DRM/KMS driver for Xilinx ZynqMP DisplayPort Subsystem")
> > Reported-by: Hulk Robot <hulkci@...wei.com>
> > Signed-off-by: Wei Yongjun <weiyongjun1@...wei.com>
>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@...asonboard.com>
>
Reviewed-by: Hyun Kwon <hyun.kwon@...inx.com>
I'll commit this to drm-misc-next-fixes soon.
Thanks,
-hyun
> > ---
> > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > index 821f7a71e182..3d53638ab15e 100644
> > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c
> > @@ -44,7 +44,7 @@ MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
> > */
> > static uint zynqmp_dp_power_on_delay_ms = 4;
> > module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444);
> > -MODULE_PARM_DESC(aux_timeout_ms, "DP power on delay in msec (default: 4)");
> > +MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
> >
> > /* Link configuration registers */
> > #define ZYNQMP_DP_LINK_BW_SET 0x0
>
> --
> Regards,
>
> Laurent Pinchart
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