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Message-ID: <20200730084219.GF3703480@smile.fi.intel.com>
Date: Thu, 30 Jul 2020 11:42:19 +0300
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Brent Lu <brent.lu@...el.com>
Cc: alsa-devel@...a-project.org,
Cezary Rojewski <cezary.rojewski@...el.com>,
Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>,
Liam Girdwood <liam.r.girdwood@...ux.intel.com>,
Jie Yang <yang.jie@...ux.intel.com>,
Mark Brown <broonie@...nel.org>,
Jaroslav Kysela <perex@...ex.cz>,
Takashi Iwai <tiwai@...e.com>,
Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>,
linux-kernel@...r.kernel.org,
Daniel Stuart <daniel.stuart14@...il.com>,
Yu-Hsuan Hsu <yuhsuan@...omium.org>,
Guennadi Liakhovetski <guennadi.liakhovetski@...ux.intel.com>,
Kai Vehmanen <kai.vehmanen@...ux.intel.com>,
Sam McNally <sammc@...omium.org>,
Damian van Soelen <dj.vsoelen@...il.com>
Subject: Re: [PATCH v2 2/2] ASoC: Intel: Add period size constraint on strago
board
On Thu, Jul 30, 2020 at 04:13:35PM +0800, Brent Lu wrote:
> From: Yu-Hsuan Hsu <yuhsuan@...omium.org>
>
> The CRAS server does not set the period size in hw_param so ALSA will
> calculate a value for period size which is based on the buffer size
> and other parameters. The value may not always be aligned with Atom's
> dsp design so a constraint is added to make sure the board always has
> a good value.
>
> Cyan uses chtmax98090 and others(banon, celes, edgar, kefka...) use
> rt5650.
Actually one more comment here.
Can you split per machine driver?
> sound/soc/intel/boards/cht_bsw_max98090_ti.c | 14 +++++++++++++-
> sound/soc/intel/boards/cht_bsw_rt5645.c | 14 +++++++++++++-
--
With Best Regards,
Andy Shevchenko
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