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Message-Id: <20200801123049.32398-7-sibis@codeaurora.org>
Date: Sat, 1 Aug 2020 18:00:48 +0530
From: Sibi Sankar <sibis@...eaurora.org>
To: robh+dt@...nel.org, georgi.djakov@...aro.org
Cc: bjorn.andersson@...aro.org, agross@...nel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-msm@...r.kernel.org, jonathan@...ek.ca,
linux-pm@...r.kernel.org, Sibi Sankar <sibis@...eaurora.org>
Subject: [PATCH 6/7] arm64: dts: qcom: sm8150: Add OSM L3 interconnect provider
Add Operation State Manager (OSM) L3 interconnect provider node on
SM8150 SoCs.
Signed-off-by: Sibi Sankar <sibis@...eaurora.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 0f6d84e8fd299..8563afd205ee9 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8150.h>
#include <dt-bindings/thermal/thermal.h>
@@ -1184,6 +1185,16 @@ apps_bcm_voter: bcm_voter {
};
};
+ osm_l3: interconnect@...21000 {
+ compatible = "qcom,sm8150-osm-l3";
+ reg = <0 0x18321000 0 0x1400>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@...23000 {
compatible = "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
--
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