linux-kernel - Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board

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Message-ID: <s5hpn873by6.wl-tiwai@suse.de>
Date:   Mon, 03 Aug 2020 18:56:33 +0200
From:   Takashi Iwai <tiwai@...e.de>
To:     "Lu, Brent" <brent.lu@...el.com>
Cc:     Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>,
        Guennadi Liakhovetski <guennadi.liakhovetski@...ux.intel.com>,
        "alsa-devel@...a-project.org" <alsa-devel@...a-project.org>,
        "Kuninori Morimoto" <kuninori.morimoto.gx@...esas.com>,
        Kai Vehmanen <kai.vehmanen@...ux.intel.com>,
        "Rojewski, Cezary" <cezary.rojewski@...el.com>,
        Jie Yang <yang.jie@...ux.intel.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Takashi Iwai <tiwai@...e.com>,
        Liam Girdwood <liam.r.girdwood@...ux.intel.com>,
        "Sam McNally" <sammc@...omium.org>,
        Mark Brown <broonie@...nel.org>,
        "Ranjani Sridharan" <ranjani.sridharan@...ux.intel.com>,
        Daniel Stuart <daniel.stuart14@...il.com>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Yu-Hsuan Hsu <yuhsuan@...omium.org>,
        Damian van Soelen <dj.vsoelen@...il.com>,
        "yuhsuan@...gle.com" <yuhsuan@...gle.com>
Subject: Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board

On Mon, 03 Aug 2020 18:45:29 +0200,
Lu, Brent wrote:
> 
> > > Hi Takashi,
> > >
> > > I've double checked with google. It's a must for Chromebooks due to
> > > low latency use case.
> > 
> > I wonder if there's a misunderstanding here?
> > 
> > I believe Takashi's question was "is this a must to ONLY accept 240 samples
> > for the period size", there was no pushback on the value itself.
> > Are those boards broken with e.g. 960 samples?
> 
> I've added google people to discuss directly.
> 
> Hi Yuhsuan,
> Would you explain why CRAS needs to use such short period size? Thanks.

For avoid further misunderstanding: it's fine that CRAS *uses* such a
short period.  It's often required for achieving a short latency.

However, the question is whether the driver can set *only* this value
for making it working.  IOW, if we don't have this constraint, what
actually happens?  If the driver gives the period size alignment,
wouldn't CRAS choose 240?


Takashi