lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 3 Aug 2020 10:16:59 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Cc:     Jiaxun Yang <jiaxun.yang@...goat.com>, linux-mips@...ux-mips.org,
        "open list:BROADCOM BMIPS MIPS ARCHITECTURE" 
        <bcm-kernel-feedback-list@...adcom.com>,
        "open list:BROADCOM BMIPS MIPS ARCHITECTURE" 
        <linux-mips@...r.kernel.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] MIPS: BMIPS: Disable pref 30 for buggy CPUs



On 8/3/2020 4:30 AM, Thomas Bogendoerfer wrote:
> On Fri, Jul 31, 2020 at 03:49:28PM -0700, Florian Fainelli wrote:
>> On 7/31/20 3:34 AM, Jiaxun Yang wrote:
>>>
>>>
>>> 在 2020/7/31 下午12:24, Florian Fainelli 写道:
>>>> Disable pref 30 by utilizing the standard quirk method and matching the
>>>> affected SoCs: 7344, 7346, 7425.
>>>>
>>>> Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
>>>> ---
>>>>   arch/mips/bmips/setup.c | 17 +++++++++++++++++
>>>>   1 file changed, 17 insertions(+)
>>>>
>>>> diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
>>>> index 19308df5f577..df0efea12611 100644
>>>> --- a/arch/mips/bmips/setup.c
>>>> +++ b/arch/mips/bmips/setup.c
>>>> @@ -110,6 +110,20 @@ static void bcm6368_quirks(void)
>>>>       bcm63xx_fixup_cpu1();
>>>>   }
>>>>   +static void bmips5000_pref30_quirk(void)
>>>> +{
>>>> +    __asm__ __volatile__(
>>>> +    "    li    $8, 0x5a455048\n"
>>>> +    "    .word    0x4088b00f\n"    /* mtc0 $8, $22, 15 */
>>>> +    "    nop; nop; nop\n"
>>>> +    "    .word    0x4008b008\n"    /* mfc0 $8, $22, 8 */
>>>> +    /* disable "pref 30" on buggy CPUs */
>>>> +    "    lui    $9, 0x0800\n"
>>>> +    "    or    $8, $9\n"
>>>> +    "    .word    0x4088b008\n"    /* mtc0 $8, $22, 8 */
>>>> +    : : : "$8", "$9");
>>>> +}
>>> Hi,
>>>
>>> Is there any toolchain issue blocking read_c0_**** family helpers being
>>> used?
>>>
>>> Use .word looks unreasonable.
>>
>> Yes, the assembler would be choking on the custom $22 selector, however
> 
> I guess you meant selector 8 and 15. If BMIPS has a 4 bit selector field
> it might be good to do a binutils patch supporting it.

Yes, sorry that is what I meant. I don't think an assembler patch makes
sense at this point given this is an isolated use, and there is not just
binutils these days, the Clang/LLVM integrated assembler would also need
to be supported, and then we would need to have the kernel say: I
require this minimum version to support the customer selectors, not
worth the trouble if you ask me.

> 
>> this patch should not be necessary given that the boot loader (CFE)
>> should have long been updated by now to disable pref 30.
> 
> so, should I add it or drop it ?

You can drop it and I would resubmit it with feedback addressed if this
later comes back.
-- 
Florian

Powered by blists - more mailing lists