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Date:   Sat, 8 Aug 2020 10:39:53 +0800
From:   Jiaxun Yang <jiaxun.yang@...goat.com>
To:     Zhou Yanjie <zhouyanjie@...yeetech.com>
Cc:     Paul Cercueil <paul@...pouillou.net>,
        Krzysztof Kozlowski <krzk@...nel.org>, od@...c.me,
        linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org,
        漆鹏振 <aric.pzqi@...enic.com>,
        dongsheng.qiu@...enic.com, rick.tyliu@...enic.com,
        yanfei.li@...enic.com, xuwanhao@...yeetech.com
Subject: Re: [PATCH 00/13] MIPS: Convert Ingenic to a generic board



在 2020/8/8 上午12:45, Paul Cercueil 写道:
> Hi Zhou,
>
> Le sam. 8 août 2020 à 0:23, Zhou Yanjie <zhouyanjie@...yeetech.com> a 
> écrit :
>> Hi Paul,
>>
>> I'm not too sure if remove "cpu-feature-overrides.h" will cause some 
>> problems for X2000, because according to my current test on X2000, I 
>> found that it is somewhat different from the SoCs using XBurst1 CPU 
>> core, with the kernel source code provided by Ingenic, for example, 
>> we must configure "#define cpu_has_tlbinv 1" in 
>> "cpu-feature-overrides.h" to make the X2000 work normally, otherwise 
>> the kernel will get stuck. And X2000's interrupt controller has also 
>> been redesigned. If these differences make it impossible to share 
>> code, should we set a subdirectory of "xburst" and "xburst2" in 
>> "arch/mips/ingenic"? (I am just worried about this situation, so far 
>> I have not been able to successfully run the mainline kernel on X2000).

Hi Yanjie,

TLBINV is a optional feature. We can always invalidate TLB via rewrite 
TLB entry. If X2000 can't work
without TLBINV it means there are some thing went wrong with TLB.
You'd better investigate in detail.

Refined interrupt controller can be enabled via DeviceTree, you only 
have to write a new irqchip driver for it.

Btw: My X2000 EVB is on the way thanks to Taobao~

Thanks.

>
> The <cpu-feature-overrides.h> is kind of a hack, to hardcode settings 
> in case the CPU is not properly detected. The cpu-probe.c should be 
> able to auto-detect these settings, including the inverted TLB that 
> the X2000 has, reading from the CPU config registers ("TLB INV" info 
> should be in config4). Right now cpu_probe_ingenic() doesn't read 
> config4 (not present on older SoCs) but that's trivial to add.
>
> As for your other question, I don't see any reason why we wouldn't be 
> able to support the X2000 aside the others in a generic kernel, so 
> don't worry :)
>
> Cheers,
> -Paul
>

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