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Message-Id: <20200811112645.24596-2-s.nawrocki@samsung.com>
Date: Tue, 11 Aug 2020 13:26:45 +0200
From: Sylwester Nawrocki <s.nawrocki@...sung.com>
To: linux-clk@...r.kernel.org
Cc: tomasz.figa@...il.com, cw00.choi@...sung.com, sboyd@...nel.org,
mturquette@...libre.com, linux-samsung-soc@...r.kernel.org,
linux-kernel@...r.kernel.org, b.zolnierkie@...sung.com,
m.szyprowski@...sung.com,
Sylwester Nawrocki <s.nawrocki@...sung.com>
Subject: [PATCH 2/2] clk: samsung: exynos5420: Avoid __clk_lookup() calls
when enabling clocks
This patch adds a clk ID to the mout_sw_aclk_g3d clk definition so related
clk pointer gets cached in the driver's private data and can be used
later instead of a __clk_lookup() call.
With that we have all clocks used in the clk_prepare_enable() calls in the
clk provider init callback cached in clk_data.hws[] and we can reference
the clk pointers directly rather than using __clk_lookup() with global names.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@...sung.com>
---
Depends on patch:
[PATCH v2] clk: samsung: Keep top BPLL mux on Exynos542x enabled
drivers/clk/samsung/clk-exynos5420.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index bd62087..06841a6 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -712,8 +712,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
SRC_TOP12, 8, 1),
MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
SRC_TOP12, 12, 1),
- MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1,
- CLK_SET_RATE_PARENT, 0),
+ MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
+ SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
SRC_TOP12, 20, 1),
MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
@@ -1649,17 +1649,18 @@ static void __init exynos5x_clk_init(struct device_node *np,
exynos5x_subcmus);
}
+ hws = ctx->clk_data.hws;
/*
* Keep top part of G3D clock path enabled permanently to ensure
* that the internal busses get their clock regardless of the
* main G3D clock enablement status.
*/
- clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d"));
+ clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk);
/*
* Keep top BPLL mux enabled permanently to ensure that DRAM operates
* properly.
*/
- clk_prepare_enable(__clk_lookup("mout_bpll"));
+ clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk);
samsung_clk_of_add_provider(np, ctx);
}
--
2.7.4
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