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Message-ID: <20200811172209.GM6967@sirena.org.uk>
Date: Tue, 11 Aug 2020 18:22:09 +0100
From: Mark Brown <broonie@...nel.org>
To: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
Cc: Yu-Hsuan Hsu <yuhsuan@...omium.org>,
Guennadi Liakhovetski <guennadi.liakhovetski@...ux.intel.com>,
"alsa-devel@...a-project.org" <alsa-devel@...a-project.org>,
Kai Vehmanen <kai.vehmanen@...ux.intel.com>,
Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
Takashi Iwai <tiwai@...e.de>,
"Rojewski, Cezary" <cezary.rojewski@...el.com>,
Takashi Iwai <tiwai@...e.com>,
Jie Yang <yang.jie@...ux.intel.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Liam Girdwood <liam.r.girdwood@...ux.intel.com>,
Sam McNally <sammc@...omium.org>,
"yuhsuan@...gle.com" <yuhsuan@...gle.com>,
Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>,
Daniel Stuart <daniel.stuart14@...il.com>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
"Lu, Brent" <brent.lu@...el.com>,
Damian van Soelen <dj.vsoelen@...il.com>
Subject: Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago
board
On Tue, Aug 11, 2020 at 11:54:38AM -0500, Pierre-Louis Bossart wrote:
> > constraint logic needs to know about this DSP limitation - it seems like
> > none of this is going to change without something new going into the
> > mix? We at least need a new question to ask about the DSP firmware I
> > think.
> I just tested aplay -Dhw: on a Cyan Chromebook with the Ubuntu kernel 5.4,
> and I see no issues with the 240 sample period. Same with 432, 960, 9600,
> etc.
> I also tried just for fun what happens with 256 samples, and I don't see any
> underflows thrown either, so I am wondering what exactly the problem is?
> Something's not adding up. I would definitively favor multiple of 1ms
> periods, since it's the only case that was productized, but there's got to
> me something a side effect of how CRAS programs the hw_params.
Is it something that goes wrong with longer playbacks possibly (eg,
someone watching a feature film or something)?
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