linux-kernel - Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board

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Message-ID: <s5hr1scz908.wl-tiwai@suse.de>
Date:   Wed, 12 Aug 2020 08:13:59 +0200
From:   Takashi Iwai <tiwai@...e.de>
To:     Yu-Hsuan Hsu <yuhsuan@...omium.org>
Cc:     Mark Brown <broonie@...nel.org>,
        Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>,
        Guennadi Liakhovetski <guennadi.liakhovetski@...ux.intel.com>,
        "alsa-devel@...a-project.org" <alsa-devel@...a-project.org>,
        Kai Vehmanen <kai.vehmanen@...ux.intel.com>,
        Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
        "Rojewski, Cezary" <cezary.rojewski@...el.com>,
        Takashi Iwai <tiwai@...e.com>,
        Jie Yang <yang.jie@...ux.intel.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Liam Girdwood <liam.r.girdwood@...ux.intel.com>,
        Sam McNally <sammc@...omium.org>,
        "yuhsuan@...gle.com" <yuhsuan@...gle.com>,
        Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>,
        Daniel Stuart <daniel.stuart14@...il.com>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        "Lu, Brent" <brent.lu@...el.com>,
        Damian van Soelen <dj.vsoelen@...il.com>
Subject: Re: [PATCH v3 2/2] ASoC: Intel: Add period size constraint on strago board

On Wed, 12 Aug 2020 05:09:58 +0200,
Yu-Hsuan Hsu wrote:
> 
> Mark Brown <broonie@...nel.org> 於 2020年8月12日 週三 上午1:22寫道：
> >
> > On Tue, Aug 11, 2020 at 11:54:38AM -0500, Pierre-Louis Bossart wrote:
> >
> > > > constraint logic needs to know about this DSP limitation - it seems like
> > > > none of this is going to change without something new going into the
> > > > mix?  We at least need a new question to ask about the DSP firmware I
> > > > think.
> >
> > > I just tested aplay -Dhw: on a Cyan Chromebook with the Ubuntu kernel 5.4,
> > > and I see no issues with the 240 sample period. Same with 432, 960, 9600,
> > > etc.
> >
> > > I also tried just for fun what happens with 256 samples, and I don't see any
> > > underflows thrown either, so I am wondering what exactly the problem is?
> > > Something's not adding up. I would definitively favor multiple of 1ms
> > > periods, since it's the only case that was productized, but there's got to
> > > me something a side effect of how CRAS programs the hw_params.
> >
> > Is it something that goes wrong with longer playbacks possibly (eg,
> > someone watching a feature film or something)?
> 
> Thanks for testing!
> 
> After doing some experiments, I think I can identify the problem more precisely.
> 1. aplay can not reproduce this issue because it writes samples
> immediately when there are some space in the buffer. However, you can
> add --test-position to see how the delay grows with period size 256.
> > aplay -Dhw:1,0 --period-size=256 --buffer-size=480 /dev/zero -d 1 -f dat --test-position
> Playing raw data '/dev/zero' : Signed 16 bit Little Endian, Rate 48000
> Hz, Stereo
> Suspicious buffer position (1 total): avail = 0, delay = 2064, buffer = 512
> Suspicious buffer position (2 total): avail = 0, delay = 2064, buffer = 512
> Suspicious buffer position (3 total): avail = 0, delay = 2096, buffer = 512
> ...

Isn't this about the alignment of the buffer size against the period
size, not the period size itself?  i.e. in the example above, the
buffer size isn't a multiple of period size, and DSP can't handle if
the position overlaps the buffer size in a half way.

If that's the problem (and it's an oft-seen restriction), the right
constraint is
  snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);


Takashi

> 2. Since many samples are moved to DSP(delay), the measured rate of
> the ring-buffer is high. (I measured it by alsa_conformance_test,
> which only test the sampling rate in the ring buffer of kernel not
> DSP)
> 
> 3. Since CRAS writes samples with a fixed frequency, this behavior
> will take all samples from the ring buffer, which is seen as underrun
> by CRAS. (It seems that it is not a real underrun because that avail
> does not larger than buffer size. Maybe CRAS should also take dalay
> into account.)
> 
> 4. In spite of it is not a real underrun, the large delay is still a
> big problem. Can we apply the constraint to fix it? Or any better
> idea?
> 
> Thanks,
> Yu-Hsuan
>