lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <aa506a3d-3e89-08ed-2d66-7098f6e5af91@codeaurora.org>
Date:   Thu, 13 Aug 2020 12:47:18 +0530
From:   Maulik Shah <mkshah@...eaurora.org>
To:     Stephen Boyd <swboyd@...omium.org>, bjorn.andersson@...aro.org,
        evgreen@...omium.org, linus.walleij@...aro.org, maz@...nel.org,
        mka@...omium.org
Cc:     linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        linux-gpio@...r.kernel.org, agross@...nel.org, tglx@...utronix.de,
        jason@...edaemon.net, dianders@...omium.org, rnayak@...eaurora.org,
        ilina@...eaurora.org, lsrao@...eaurora.org
Subject: Re: [PATCH v4 2/7] pinctrl: qcom: Use return value from irq_set_wake
 call

Hi,

On 8/12/2020 1:04 AM, Stephen Boyd wrote:
> Quoting Maulik Shah (2020-08-10 04:20:55)
>> msmgpio irqchip is not using return value of irq_set_wake call.
>> Start using it.
> Does this work when the irq parent isn't setup in a hierarchy?
yes it works fine even when parent isn't setup in hierarchy.
> I seem to
> recall that this was written this way because sometimes
> irq_set_irq_wake() would fail for the summary irq so it was a best
> effort setting of wake on the summary line.
Thanks for pointing this.

It was written this way since previously GIC driver neither had 
IRQCHIP_SKIP_SET_WAKE flag nor it implemented .irq_set_wake callback,

so the call to irq_set_irq_wake() to set_irq_wake_real() used to return 
error -ENXIO in past.

I see this is already taken care now in GIC drivers by adding 
IRQCHIP_SKIP_SET_WAKE flag.

>
>> Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy")
>> Signed-off-by: Maulik Shah <mkshah@...eaurora.org>
>> Reviewed-by: Douglas Anderson <dianders@...omium.org>
>> ---
>>   drivers/pinctrl/qcom/pinctrl-msm.c | 8 +++-----
>>   1 file changed, 3 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
>> index 90edf61..c264561 100644
>> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
>> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
>> @@ -1077,12 +1077,10 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
>>           * when TLMM is powered on. To allow that, enable the GPIO
>>           * summary line to be wakeup capable at GIC.
>>           */
>> -       if (d->parent_data)
>> -               irq_chip_set_wake_parent(d, on);
>> -
>> -       irq_set_irq_wake(pctrl->irq, on);
>> +       if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
>> +               return irq_chip_set_wake_parent(d, on);
> So this bit is probably fine.
>
>>   
>> -       return 0;
>> +       return irq_set_irq_wake(pctrl->irq, on);
> But this one is probably not fine.

As per above both of them are fine.

Thanks,
Maulik

>
>>   }
>>   
>>   static int msm_gpio_irq_reqres(struct irq_data *d)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ