lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 13 Aug 2020 10:45:45 +0200
From:   Oliver Graute <oliver.graute@...oconnector.com>
To:     aisheng.dong@....com
Cc:     fabio.estevam@....com, kernel@...gutronix.de, linux-imx@....com,
        linux-arm-kernel@...ts.infradead.org,
        Oliver Graute <oliver.graute@...oconnector.com>,
        Rob Herring <robh+dt@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [RFC] arm64: dts: imx8qm: added lvds pwm

Hello Aisheng,

I tried to add lvds pwm to imx8qm.dtsi to get backlight working. But without
success. I'am running into this issue:

[    0.858737]  lcd0-pwm0: failed to power up resource 188 ret -22

Can you review and comment please?

This patch is based on your patch series.

Best regards,

Oliver

---
 arch/arm64/boot/dts/freescale/imx8qm.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index fd0e706ea011..cf9aea4b26f4 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -137,6 +137,22 @@ hsio: hsio@...80000 {
 		reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
 	};
 
+
+	lvds1_pwm: pwm@...44000 {
+		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x57244000 0x1000>;
+		clocks = <&pwm0_lpcg IMX_LPCG_CLK_4>,
+			 <&pwm0_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+		status = "disabled";
+	};
+
 	pmu {
 		compatible = "arm,armv8-pmuv3";
 		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.26.0

Powered by blists - more mailing lists