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Message-Id: <1597406966-13740-7-git-send-email-abel.vesa@nxp.com>
Date: Fri, 14 Aug 2020 15:09:15 +0300
From: Abel Vesa <abel.vesa@....com>
To: Mike Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <kernel@...gutronix.de>,
Fabio Estevam <fabio.estevam@....com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Anson Huang <anson.huang@....com>,
Jacky Bai <ping.bai@....com>, Peng Fan <peng.fan@....com>,
Dong Aisheng <aisheng.dong@....com>,
Fugang Duan <fugang.duan@....com>, devicetree@...r.kernel.org
Cc: NXP Linux Team <linux-imx@....com>,
linux-arm-kernel@...ts.infradead.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-clk@...r.kernel.org, Abel Vesa <abel.vesa@....com>
Subject: [PATCH v2 06/17] dt-bindings: clock: imx8mp: Add hdmi blk_ctrl clock IDs
These will be used by the imx8mp for blk-ctrl driver.
Signed-off-by: Abel Vesa <abel.vesa@....com>
Acked-by: Rob Herring <robh@...nel.org>
---
include/dt-bindings/clock/imx8mp-clock.h | 40 ++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index bb465a7..6b90831 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -396,6 +396,46 @@
#define IMX8MP_CLK_AUDIO_BLK_CTRL_END 59
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_APB_CLK 0
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_B_CLK 1
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_REF266M_CLK 2
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL24M_CLK 3
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL32K_CLK 4
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_TX_PIX_CLK 5
+#define IMX8MP_CLK_HDMI_BLK_CTRL_IRQS_STEER_CLK 6
+#define IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDMI_CLK 7
+#define IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDCP_CLK 8
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_APB_CLK 9
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_B_CLK 10
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PDI_CLK 11
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PIX_CLK 12
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_SPU_CLK 13
+#define IMX8MP_CLK_HDMI_BLK_CTRL_FDCC_REF_CLK 14
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_APB_CLK 15
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_B_CLK 16
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_CEA_CLK 17
+#define IMX8MP_CLK_HDMI_BLK_CTRL_VSFD_CEA_CLK 18
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_HPI_CLK 19
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_APB_CLK 20
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_CEC_CLK 21
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_ESM_CLK 22
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_GPA_CLK 23
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIXEL_CLK 24
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SFR_CLK 25
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SKP_CLK 26
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PREP_CLK 27
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_APB_CLK 28
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_INT_CLK 29
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SEC_MEM_CLK 30
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_SKP_CLK 31
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_VID_LINK_PIX_CLK 32
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_APB_CLK 33
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HTXPHY_CLK_SEL 34
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_CLK_SEL 35
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIPE_CLK_SEL 36
+
+#define IMX8MP_CLK_HDMI_BLK_CTRL_END 37
+
#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK 0
#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF 1
#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_PCLK 2
--
2.7.4
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