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Date:   Fri, 14 Aug 2020 19:43:32 +0200
From:   Stephan Gerhold <stephan@...hold.net>
To:     Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Cc:     broonie@...nel.org, alsa-devel@...a-project.org,
        linux-kernel@...r.kernel.org, lgirdwood@...il.com, tiwai@...e.com,
        john.stultz@...aro.org
Subject: Re: [PATCH] ASoC: msm8916-wcd-analog: fix register Interrupt offset

On Tue, Aug 11, 2020 at 11:34:52AM +0100, Srinivas Kandagatla wrote:
> For some reason interrupt set and clear register offsets are
> not set correctly.
> This patch corrects them!
> 
> Fixes: 585e881e5b9e ("ASoC: codecs: Add msm8916-wcd analog codec")
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
> ---
>  sound/soc/codecs/msm8916-wcd-analog.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/sound/soc/codecs/msm8916-wcd-analog.c b/sound/soc/codecs/msm8916-wcd-analog.c
> index 4428c62e25cf..3ddd822240e3 100644
> --- a/sound/soc/codecs/msm8916-wcd-analog.c
> +++ b/sound/soc/codecs/msm8916-wcd-analog.c
> @@ -19,8 +19,8 @@
>  
>  #define CDC_D_REVISION1			(0xf000)
>  #define CDC_D_PERPH_SUBTYPE		(0xf005)
> -#define CDC_D_INT_EN_SET		(0x015)
> -#define CDC_D_INT_EN_CLR		(0x016)
> +#define CDC_D_INT_EN_SET		(0xf015)
> +#define CDC_D_INT_EN_CLR		(0xf016)
>  #define MBHC_SWITCH_INT			BIT(7)
>  #define MBHC_MIC_ELECTRICAL_INS_REM_DET	BIT(6)
>  #define MBHC_BUTTON_PRESS_DET		BIT(5)
> -- 
> 2.21.0
> 

It's surprising that we didn't notice this before. Seems like the HW
has exactly the IRQs we want enabled by default. Everything seems to be
still working fine after this patch, so FWIW:

Tested-by: Stephan Gerhold <stephan@...hold.net>
Reviewed-by: Stephan Gerhold <stephan@...hold.net>

Thanks!
Stephan

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