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Message-Id: <20200815182223.408965-1-martin.blumenstingl@googlemail.com>
Date: Sat, 15 Aug 2020 20:22:23 +0200
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: linux-amlogic@...ts.infradead.org, khilman@...libre.com
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Subject: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node
All IO mapped SoC peripherals should be within the "soc" node. Move the
L2 cache-controller there as well since it's the only one not following
this pattern.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
---
arch/arm/boot/dts/meson.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index eadb0832bcfc..7649dd1e0b9e 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -11,13 +11,6 @@ / {
#size-cells = <1>;
interrupt-parent = <&gic>;
- L2: cache-controller@...00000 {
- compatible = "arm,pl310-cache";
- reg = <0xc4200000 0x1000>;
- cache-unified;
- cache-level = <2>;
- };
-
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -172,6 +165,13 @@ timer_abcde: timer@...0 {
};
};
+ L2: cache-controller@...00000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xc4200000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
periph: bus@...00000 {
compatible = "simple-bus";
reg = <0xc4300000 0x10000>;
--
2.28.0
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