| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <7fe337fa-abbc-82be-c8e8-b9e2a6179b90@redhat.com>
Date: Sun, 16 Aug 2020 14:01:03 +0200
From: Auger Eric <eric.auger@...hat.com>
To: Liu Yi L <yi.l.liu@...el.com>, alex.williamson@...hat.com,
baolu.lu@...ux.intel.com, joro@...tes.org
Cc: kevin.tian@...el.com, jacob.jun.pan@...ux.intel.com,
ashok.raj@...el.com, jun.j.tian@...el.com, yi.y.sun@...el.com,
jean-philippe@...aro.org, peterx@...hat.com, hao.wu@...el.com,
stefanha@...il.com, iommu@...ts.linux-foundation.org,
kvm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6 15/15] iommu/vt-d: Support reporting nesting capability
info
Hi Yi,
On 7/28/20 8:27 AM, Liu Yi L wrote:
> This patch reports nesting info, and only supports the case where all
> the physical iomms have the same CAP/ECAP MASKS.
s/iomms/iommus
>
> Cc: Kevin Tian <kevin.tian@...el.com>
> CC: Jacob Pan <jacob.jun.pan@...ux.intel.com>
> Cc: Alex Williamson <alex.williamson@...hat.com>
> Cc: Eric Auger <eric.auger@...hat.com>
> Cc: Jean-Philippe Brucker <jean-philippe@...aro.org>
> Cc: Joerg Roedel <joro@...tes.org>
> Cc: Lu Baolu <baolu.lu@...ux.intel.com>
> Signed-off-by: Liu Yi L <yi.l.liu@...el.com>
> Signed-off-by: Jacob Pan <jacob.jun.pan@...ux.intel.com>
> ---
> v2 -> v3:
> *) remove cap/ecap_mask in iommu_nesting_info.
> ---
> drivers/iommu/intel/iommu.c | 81 +++++++++++++++++++++++++++++++++++++++++++--
> include/linux/intel-iommu.h | 16 +++++++++
> 2 files changed, 95 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 88f4647..0835804 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -5660,12 +5660,16 @@ static inline bool iommu_pasid_support(void)
> static inline bool nested_mode_support(void)
> {
> struct dmar_drhd_unit *drhd;
> - struct intel_iommu *iommu;
> + struct intel_iommu *iommu, *prev = NULL;
> bool ret = true;
>
> rcu_read_lock();
> for_each_active_iommu(iommu, drhd) {
> - if (!sm_supported(iommu) || !ecap_nest(iommu->ecap)) {
> + if (!prev)
> + prev = iommu;
> + if (!sm_supported(iommu) || !ecap_nest(iommu->ecap) ||
> + (VTD_CAP_MASK & (iommu->cap ^ prev->cap)) ||
> + (VTD_ECAP_MASK & (iommu->ecap ^ prev->ecap))) {
> ret = false;
> break;
So this changes the behavior of DOMAIN_ATTR_NESTING. Shouldn't it have a
Fixes tag as well? And maybe add the capability getter in a separate patch?
> }
> @@ -6081,6 +6085,78 @@ intel_iommu_domain_set_attr(struct iommu_domain *domain,
> return ret;
> }
>
> +static int intel_iommu_get_nesting_info(struct iommu_domain *domain,
> + struct iommu_nesting_info *info)
> +{
> + struct dmar_domain *dmar_domain = to_dmar_domain(domain);
> + u64 cap = VTD_CAP_MASK, ecap = VTD_ECAP_MASK;
> + struct device_domain_info *domain_info;
> + struct iommu_nesting_info_vtd vtd;
> + unsigned long flags;
> + unsigned int size;
> +
> + if (domain->type != IOMMU_DOMAIN_UNMANAGED ||
> + !(dmar_domain->flags & DOMAIN_FLAG_NESTING_MODE))
> + return -ENODEV;
> +
> + if (!info)
> + return -EINVAL;
> +
> + size = sizeof(struct iommu_nesting_info) +
> + sizeof(struct iommu_nesting_info_vtd);
> + /*
> + * if provided buffer size is smaller than expected, should
> + * return 0 and also the expected buffer size to caller.
> + */
> + if (info->argsz < size) {
> + info->argsz = size;
> + return 0;
> + }
> +
> + spin_lock_irqsave(&device_domain_lock, flags);
> + /*
> + * arbitrary select the first domain_info as all nesting
> + * related capabilities should be consistent across iommu
> + * units.
> + */
> + domain_info = list_first_entry(&dmar_domain->devices,
> + struct device_domain_info, link);
> + cap &= domain_info->iommu->cap;
> + ecap &= domain_info->iommu->ecap;
> + spin_unlock_irqrestore(&device_domain_lock, flags);
> +
> + info->format = IOMMU_PASID_FORMAT_INTEL_VTD;
> + info->features = IOMMU_NESTING_FEAT_SYSWIDE_PASID |
> + IOMMU_NESTING_FEAT_BIND_PGTBL |
> + IOMMU_NESTING_FEAT_CACHE_INVLD;
> + info->addr_width = dmar_domain->gaw;
> + info->pasid_bits = ilog2(intel_pasid_max_id);
> + info->padding = 0;
> + vtd.flags = 0;
> + vtd.padding = 0;
> + vtd.cap_reg = cap;
> + vtd.ecap_reg = ecap;
> +
> + memcpy(info->data, &vtd, sizeof(vtd));
> + return 0;
> +}
> +
> +static int intel_iommu_domain_get_attr(struct iommu_domain *domain,
> + enum iommu_attr attr, void *data)
> +{
> + switch (attr) {
> + case DOMAIN_ATTR_NESTING:
> + {
> + struct iommu_nesting_info *info =
> + (struct iommu_nesting_info *)data;
don't you need to hold a device_domain_lock earlier to make sure domain
attributes can't change behind your back (unmanaged type and nested mode)?
> +
> + return intel_iommu_get_nesting_info(domain, info);
> + }
> + default:
> + return -ENOENT;
> + }
> +}
> +
> /*
> * Check that the device does not live on an external facing PCI port that is
> * marked as untrusted. Such devices should not be able to apply quirks and
> @@ -6103,6 +6179,7 @@ const struct iommu_ops intel_iommu_ops = {
> .domain_alloc = intel_iommu_domain_alloc,
> .domain_free = intel_iommu_domain_free,
> .domain_set_attr = intel_iommu_domain_set_attr,
> + .domain_get_attr = intel_iommu_domain_get_attr,
> .attach_dev = intel_iommu_attach_device,
> .detach_dev = intel_iommu_detach_device,
> .aux_attach_dev = intel_iommu_aux_attach_device,
> diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
> index f98146b..5acf795 100644
> --- a/include/linux/intel-iommu.h
> +++ b/include/linux/intel-iommu.h
> @@ -197,6 +197,22 @@
> #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
> #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
>
> +/* Nesting Support Capability Alignment */
> +#define VTD_CAP_FL1GP BIT_ULL(56)
> +#define VTD_CAP_FL5LP BIT_ULL(60)
> +#define VTD_ECAP_PRS BIT_ULL(29)
> +#define VTD_ECAP_ERS BIT_ULL(30)
> +#define VTD_ECAP_SRS BIT_ULL(31)
> +#define VTD_ECAP_EAFS BIT_ULL(34)
> +#define VTD_ECAP_PASID BIT_ULL(40)
> +
> +/* Only capabilities marked in below MASKs are reported */
> +#define VTD_CAP_MASK (VTD_CAP_FL1GP | VTD_CAP_FL5LP)
> +
> +#define VTD_ECAP_MASK (VTD_ECAP_PRS | VTD_ECAP_ERS | \
> + VTD_ECAP_SRS | VTD_ECAP_EAFS | \
> + VTD_ECAP_PASID)
> +
> /* Virtual command interface capability */
> #define vccap_pasid(v) (((v) & DMA_VCS_PAS)) /* PASID allocation */
>
>
Thanks
Eric
Powered by blists - more mailing lists