linux-kernel - [PATCH 2/3] arm64: dts: rockchip: rk3328 usb3 controller node

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Message-ID: <MEsGppx--3-2@tutanota.com>
Date:   Sun, 16 Aug 2020 19:18:13 +0200 (CEST)
From:   Cameron Nemo <cnemo@...anota.com>
To:     Devicetree <devicetree@...r.kernel.org>,
        Linux Arm Kernel <linux-arm-kernel@...ts.infradead.org>,
        Linux Rockchip <linux-rockchip@...ts.infradead.org>,
        Linux Kernel <linux-kernel@...r.kernel.org>,
        Linux Usb <linux-usb@...r.kernel.org>
Cc:     Robh+dt <robh+dt@...nel.org>, Heiko <heiko@...ech.de>,
        Balbi <balbi@...nel.org>, Gregkh <gregkh@...uxfoundation.org>
Subject: [PATCH 2/3] arm64: dts: rockchip: rk3328 usb3 controller node

RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3
core's general architecture. It can act as static xHCI host
controller, static device controller, USB 3.0/2.0 OTG basing
on ID of USB3.0 PHY.

Signed-off-by: William Wu <william.wu@...k-chips.com>
Signed-off-by: Heiko Stuebner <heiko@...ech.de>
Signed-off-by: Cameron Nemo <cnemo@...anota.com>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index bbdb19a3e85d..27e86bf06d3e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -983,6 +983,33 @@ usb_host0_ohci: usb@...d0000 {
status = "disabled";
};

+	usbdrd3: usb@...00000 {
+		compatible = "rockchip,rk3328-dwc3";
+		clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+			 <&cru ACLK_USB3OTG>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		usbdrd_dwc3: dwc3@...00000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xff600000 0x0 0x100000>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "otg";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			status = "disabled";
+		};
+	};
+
gic: interrupt-controller@...11000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.28.0