linux-kernel - Re: [PATCH] PCI: designware-ep: Fix the Header Type check

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Message-ID: <202008161131.glXwp5eA%lkp@intel.com>
Date:   Sun, 16 Aug 2020 11:55:51 +0800
From:   kernel test robot <lkp@...el.com>
To:     Zhiqiang Hou <Zhiqiang.Hou@....com>, linux-kernel@...r.kernel.org,
        linux-pci@...r.kernel.org, lorenzo.pieralisi@....com,
        robh@...nel.org, bhelgaas@...gle.com, amurray@...goodpenguin.co.uk,
        jingoohan1@...il.com, gustavo.pimentel@...opsys.com
Cc:     kbuild-all@...ts.01.org, Hou Zhiqiang <Zhiqiang.Hou@....com>
Subject: Re: [PATCH] PCI: designware-ep: Fix the Header Type check

Hi Zhiqiang,

I love your patch! Perhaps something to improve:

[auto build test WARNING on pci/next]
[also build test WARNING on linux/master linus/master v5.8 next-20200814]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Zhiqiang-Hou/PCI-designware-ep-Fix-the-Header-Type-check/20200814-161623
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: alpha-allyesconfig (attached as .config)
compiler: alpha-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=alpha 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>

All warnings (new ones prefixed by >>):

   drivers/pci/controller/dwc/pcie-designware-ep.c: In function 'dw_pcie_ep_init_complete':
>> drivers/pci/controller/dwc/pcie-designware-ep.c:509:15: warning: suggest parentheses around comparison in operand of '&' [-Wparentheses]
     509 |  if (hdr_type & 0x7f != PCI_HEADER_TYPE_NORMAL) {
         |               ^

vim +509 drivers/pci/controller/dwc/pcie-designware-ep.c

   498	
   499	int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
   500	{
   501		struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
   502		unsigned int offset;
   503		unsigned int nbars;
   504		u8 hdr_type;
   505		u32 reg;
   506		int i;
   507	
   508		hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
 > 509		if (hdr_type & 0x7f != PCI_HEADER_TYPE_NORMAL) {
   510			dev_err(pci->dev,
   511				"PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
   512				hdr_type);
   513			return -EIO;
   514		}
   515	
   516		ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
   517	
   518		ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
   519	
   520		offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
   521		if (offset) {
   522			reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
   523			nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
   524				PCI_REBAR_CTRL_NBAR_SHIFT;
   525	
   526			dw_pcie_dbi_ro_wr_en(pci);
   527			for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
   528				dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
   529			dw_pcie_dbi_ro_wr_dis(pci);
   530		}
   531	
   532		dw_pcie_setup(pci);
   533	
   534		return 0;
   535	}
   536	EXPORT_SYMBOL_GPL(dw_pcie_ep_init_complete);
   537	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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