linux-kernel - [PATCH 5/7] MIPS: cevt-r4k: Don't handle IRQ if clockevent is not enabled

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Message-Id: <20200817034701.3515721-6-jiaxun.yang@flygoat.com>
Date:   Mon, 17 Aug 2020 11:46:44 +0800
From:   Jiaxun Yang <jiaxun.yang@...goat.com>
To:     linux-mips@...r.kernel.org
Cc:     Jiaxun Yang <jiaxun.yang@...goat.com>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Huacai Chen <chenhc@...ote.com>,
        Aleksandar Markovic <aleksandar.qemu.devel@...il.com>,
        Serge Semin <Sergey.Semin@...kalelectronics.ru>,
        Paul Burton <paulburton@...nel.org>,
        WANG Xuerui <git@...0n.name>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        周琰杰 (Zhou Yanjie) 
        <zhouyanjie@...yeetech.com>,
        Liangliang Huang <huanglllzu@...il.com>,
        afzal mohammed <afzal.mohd.ma@...il.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>,
        Peter Xu <peterx@...hat.com>,
        Sergey Korolev <s.korolev@...systems.com>,
        Marc Zyngier <maz@...nel.org>, Anup Patel <anup.patel@....com>,
        Herbert Xu <herbert@...dor.apana.org.au>,
        Steven Price <steven.price@....com>,
        Atish Patra <atish.patra@....com>,
        Ming Lei <ming.lei@...hat.com>,
        Daniel Jordan <daniel.m.jordan@...cle.com>,
        Mike Leach <mike.leach@...aro.org>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Subject: [PATCH 5/7] MIPS: cevt-r4k: Don't handle IRQ if clockevent is not enabled

Some platforms may have shared Cause.TI, bailing out in IRQ handler
when clock event is not enabled can give another clock device a chance.

Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com>
---
 arch/mips/kernel/cevt-r4k.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index f0c52d751d0a..d396b1011fee 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -142,6 +142,15 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
 	if (handle_perf_irq(r2))
 		return IRQ_HANDLED;
 
+	cd = &per_cpu(mips_clockevent_device, cpu);
+	/*
+	 * If the clockevent have not enabled, then no need to check the rest.
+	 * Some platforms may have shared Cause.TI, bailing out here can
+	 * give another clock device a chance.
+	 */
+	if (clockevent_state_detached(cd) || clockevent_state_shutdown(cd))
+		return IRQ_NONE;
+
 	/*
 	 * The same applies to performance counter interrupts.	But with the
 	 * above we now know that the reason we got here must be a timer
@@ -150,7 +159,6 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
 	if (!r2 || (read_c0_cause() & CAUSEF_TI)) {
 		/* Clear Count/Compare Interrupt */
 		write_c0_compare(read_c0_compare());
-		cd = &per_cpu(mips_clockevent_device, cpu);
 		cd->event_handler(cd);
 
 		return IRQ_HANDLED;
-- 
2.28.0.rc1