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Date: Mon, 17 Aug 2020 09:34:17 +0530 From: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org> To: Andy Gross <agross@...nel.org>, Bjorn Andersson <bjorn.andersson@...aro.org>, Stephen Boyd <swboyd@...omium.org> Cc: linux-arm-msm@...r.kernel.org, Douglas Anderson <dianders@...omium.org>, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org> Subject: [PATCH] arm64: dts: qcom: sc7180: Fix the LLCC base register size There is only one LLCC logical bank on SC7180 SoC of size 0x50000(320KB) not 2MB, so correct the size and fix copy paste mistake from SDM845 which had 4 logical banks. Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order") Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node") Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org> --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index d46b3833e52f..e875f6c3b663 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2618,7 +2618,7 @@ dc_noc: interconnect@...0000 { system-cache-controller@...0000 { compatible = "qcom,sc7180-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; + reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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