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Message-Id: <20200819182645.30132-1-f.fainelli@gmail.com>
Date:   Wed, 19 Aug 2020 11:26:43 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     linux-mips@...ux-mips.org
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Huacai Chen <chenhc@...ote.com>,
        Paul Burton <paulburton@...nel.org>,
        Jiaxun Yang <jiaxun.yang@...goat.com>,
        Mike Rapoport <rppt@...nel.org>,
        Liangliang Huang <huanglllzu@...il.com>,
        Oleksij Rempel <linux@...pel-privat.de>,
        Kamal Dasu <kdasu.kdev@...il.com>,
        Ralf Baechle <ralf@...ux-mips.org>,
        bcm-kernel-feedback-list@...adcom.com (open list:BROADCOM BMIPS MIPS
        ARCHITECTURE),
        linux-mips@...r.kernel.org (open list:BROADCOM BMIPS MIPS ARCHITECTURE),
        linux-kernel@...r.kernel.org (open list)
Subject: [PATCH mips-fixes 0/2] MIPS: BMIPS: couple of fixes

Hi Thomas,

These two patches are fixes for the BMIPS5000/5200 CPU cores which were
missing an inclusive physical cache setting from the cpuinfo structure
and we would not be calling CPU specific initialization for secondarey
cores on the second hardware thread.

Thanks!

Florian Fainelli (2):
  MIPS: mm: BMIPS5000 has inclusive physical caches
  MIPS: BMIPS: Also call bmips_cpu_setup() for secondary cores

 arch/mips/kernel/smp-bmips.c | 2 ++
 arch/mips/mm/c-r4k.c         | 4 ++++
 2 files changed, 6 insertions(+)

-- 
2.17.1

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