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Message-Id: <20200819182645.30132-2-f.fainelli@gmail.com>
Date: Wed, 19 Aug 2020 11:26:44 -0700
From: Florian Fainelli <f.fainelli@...il.com>
To: linux-mips@...ux-mips.org
Cc: Florian Fainelli <f.fainelli@...il.com>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Huacai Chen <chenhc@...ote.com>,
Paul Burton <paulburton@...nel.org>,
Jiaxun Yang <jiaxun.yang@...goat.com>,
Mike Rapoport <rppt@...nel.org>,
Liangliang Huang <huanglllzu@...il.com>,
Oleksij Rempel <linux@...pel-privat.de>,
Kamal Dasu <kdasu.kdev@...il.com>,
Ralf Baechle <ralf@...ux-mips.org>,
bcm-kernel-feedback-list@...adcom.com (open list:BROADCOM BMIPS MIPS
ARCHITECTURE),
linux-mips@...r.kernel.org (open list:BROADCOM BMIPS MIPS ARCHITECTURE),
linux-kernel@...r.kernel.org (open list)
Subject: [PATCH mips-fixes 1/2] MIPS: mm: BMIPS5000 has inclusive physical caches
When the BMIPS generic cpu-feature-overrides.h file was introduced,
cpu_has_inclusive_caches/MIPS_CPU_INCLUSIVE_CACHES was not set for
BMIPS5000 CPUs. Correct this when we have initialized the MIPS secondary
cache successfully.
Fixes: f337967d6d87 ("MIPS: BMIPS: Add cpu-feature-overrides.h")
Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
---
arch/mips/mm/c-r4k.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fc5a6d25f74f..0ef717093262 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1712,7 +1712,11 @@ static void setup_scache(void)
printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
scache_size >> 10,
way_string[c->scache.ways], c->scache.linesz);
+
+ if (current_cpu_type() == CPU_BMIPS5000)
+ c->options |= MIPS_CPU_INCLUSIVE_CACHES;
}
+
#else
if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
--
2.17.1
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