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Message-ID: <CAL_JsqLtGF57Q3FEjFWhDkdwSwp6S4SERAG9AwuB-eEb=xtMKw@mail.gmail.com>
Date: Fri, 21 Aug 2020 16:11:22 -0600
From: Rob Herring <robh+dt@...nel.org>
To: Hongtao Wu <wuht06@...il.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Orson Zhai <orsonzhai@...il.com>,
Baolin Wang <baolin.wang7@...il.com>,
Chunyan Zhang <zhang.lyra@...il.com>,
PCI <linux-pci@...r.kernel.org>, devicetree@...r.kernel.org,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Billows Wu <billows.wu@...soc.com>
Subject: Re: [PATCH 1/2] dt-bindings: PCI: sprd: Document Unisoc PCIe RC host controller
On Fri, Aug 21, 2020 at 3:52 AM Hongtao Wu <wuht06@...il.com> wrote:
>
> From: Billows Wu <billows.wu@...soc.com>
>
> This series adds PCIe bindings for Uisoc SoCs.
typo
> This controller is based on DesignWare PCIe IP.
>
> Signed-off-by: Billows Wu <billows.wu@...soc.com>
> ---
> .../devicetree/bindings/pci/sprd-pcie.yaml | 88 ++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/sprd-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/sprd-pcie.yaml b/Documentation/devicetree/bindings/pci/sprd-pcie.yaml
> new file mode 100644
> index 0000000..6eab4b8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/sprd-pcie.yaml
> @@ -0,0 +1,88 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/sprd-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SoC PCIe Host Controller Device Tree Bindings
> +
> +maintainers:
> + - Billows Wu <billows.wu@...soc.com>
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
> + - $ref: "sprd-pcie.yaml#"
Drop this. You don't need to include yourself.
> +
> +properties:
> + compatible:
> + items:
> + - const: sprd,pcie
> + - const: sprd,pcie-ep
> +
> + reg:
> + minItems: 2
> + maxItems: 3
> + items:
> + - description: Controller control and status registers.
> + - description: PCIe shadow registers.
> + - description: PCIe configuration registers.
> +
> + reg-names:
> + items:
> + - const: dbi
> + - const: dbi2
> + - const: cfg
'config' is the standard name.
> +
> + ranges:
> + maxItems: 2
> +
> + num-lanes:
> + maxItems: 1
maxItems is for arrays and this is not an array. How many lanes are valid?
enum: [ 1, 2, 27?, ... ]
> + description: Number of lanes to use for this port.
> +
> + num-ib-windows:
> + maxItems: 1
Not an array.
> + description: Number of inbound windows to use for this port.
> +
> + num-ob-windows:
> + maxItems: 1
Not an array.
> + description: Number of outbound windows to use for this port.
> +
> + bus-range:
> + description: Range of bus numbers associated with this controller.
Drop if you don't have constraints.
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-names:
> + maxItems: 1
Need to define the name, though you don't really need this with only 1.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - num-lanes
> + - ranges
> + - bus-range
> + - interrupts
> + - interrupt-names
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + pcie0@...00000 {
> + compatible = "sprd,pcie", "snps,dw-pcie";
Didn't document "snps,dw-pcie". You'll need a custom 'select' to avoid
selecting all instances of "snps,dw-pcie".
> + reg = <0x0 0x2b100000 0x0 0x2000>,
> + <0x2 0x00000000 0x0 0x2000>;
> + reg-names = "dbi", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges = <0x01000000 0x0 0x00000000 0x2 0x00002000 0x0 0x00010000
> + 0x03000000 0x0 0x10000000 0x2 0x10000000 0x1 0xefffffff>;
> + bus-range = <0 15>;
> + num-lanes = <1>;
> + num-viewport = <8>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + };
> --
> 2.7.4
>
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