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Date:   Sat, 22 Aug 2020 09:42:16 -0700
From:   Andy Lutomirski <>
To:     Paolo Bonzini <>
Cc:     Borislav Petkov <>,
        Sean Christopherson <>,
        Andy Lutomirski <>,
        Thomas Gleixner <>,
        Ingo Molnar <>, X86 ML <>,
        "H. Peter Anvin" <>,
        LKML <>,
        Dave Hansen <>,
        Chang Seok Bae <>,
        Peter Zijlstra <>,
        Sasha Levin <>,
        kvm list <>,
        Tom Lendacky <>
Subject: Re: [PATCH] x86/entry/64: Disallow RDPID in paranoid entry if KVM is enabled

On Fri, Aug 21, 2020 at 3:07 AM Paolo Bonzini <> wrote:
> On 21/08/20 11:48, Borislav Petkov wrote:
> >> It's not like we grab MSRs every day.  The user-return notifier restores
> >> 6 MSRs (7 on very old processors).  The last two that were added were
> >> MSR_TSC_AUX itself in 2009 (!) and MSR_IA32_TSX_CTRL last year.
> > What about "If it is a shared resource, there better be an agreement
> > about sharing it." is not clear?
> >
> > It doesn't matter how many or which resources - there needs to be a
> > contract for shared use so that shared use is possible. It is that
> > simple.
> Sure, and I'll make sure to have that discussion the next time we add a
> shared MSR in 2029.
> In the meanwhile:
> * for the syscall MSRs, patches to share them were reviewed by hpa and
> peterz so I guess there's no problem.
> * for MSR_TSC_AUX, which is the one that is causing problems, everybody
> seems to agree with just using LSL (in the lack specific numbers on
> performance improvements from RDPID).
> * for MSR_IA32_TSX_CTRL.RTM_DISABLE, which is the only one that was
> added in the last 10 years, I'm pretty sure there are no plans for using
> the Trusty Sidechannel eXtension in the kernel.  So that should be fine
> too.  (The CPUID_CLEAR bit of the MSR is not shared).

Regardless of how anyone feels about who owns what in arch/x86 vs
arch/x86/kvm, the x86 architecture is a mess that comes from Intel and
AMD, and we have to deal with it.  On VMX, when a VM exits, the VM's
value of MSR_TSC_AUX is live, and we can take an NMI, MCE, or
abominable new #SX, #VE, #VC, etc on the next instruction boundary.
And unless we use the atomic MSR switch mechanism, the result is that
we're going through the entry path with guest-controlled MSRs.

So I think we can chalk this one up to obnoxious hardware.

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