linux-kernel - Re: [PATCH 00/13] MIPS: Convert Ingenic to a generic board

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Message-ID: <alpine.LFD.2.21.2008220310130.3460685@eddie.linux-mips.org>
Date:   Sat, 22 Aug 2020 03:29:36 +0100 (BST)
From:   "Maciej W. Rozycki" <macro@...ux-mips.org>
To:     Paul Cercueil <paul@...pouillou.net>
cc:     Zhou Yanjie <zhouyanjie@...yeetech.com>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Paul Burton <paulburton@...nel.org>,
        Krzysztof Kozlowski <krzk@...nel.org>, od@...c.me,
        linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org,
        漆鹏振 <aric.pzqi@...enic.com>,
        dongsheng.qiu@...enic.com, rick.tyliu@...enic.com,
        yanfei.li@...enic.com, xuwanhao@...yeetech.com
Subject: Re: [PATCH 00/13] MIPS: Convert Ingenic to a generic board

Hi Paul,

> > FAOD <cpu-feature-overrides.h> is not a hack, but an optimisation measure
> > so that features known to be hardwired for a given machine/CPU do not have
> > to be dynamically queried every time referred.  In some cases that results
> > in large portions of code being optimised away by the compiler as well.
> 
> Fair enough. Bloat-o-meter reports about ~100 KiB saved when that file is
> present. But we can't use it in a generic kernel, unfortunately.

 Well, run-time patching might be an alternative to get the best of both 
worlds, but someone would have to reimplement our feature selection system 
to use it.

> > The hardcoded value for a feature defined in <cpu-feature-overrides.h>
> > always has to be the same as one in the corresponding bit of the `options'
> > member of `struct cpuinfo_mips', in this case MIPS_CPU_TLBINV.
> 
> In theory yes, in practice the CPU detection code is lagging behind...

 I wasn't aware of that.  In that case it has been a design abuse which 
has been missed by the maintainer when accepting patches.  It used to be 
the case that run-time detection was accurate and overrides were rather 
lazily added.

 Also I note Ingenic must have had a CPU erratum if our `decode_configs' 
doesn't just work, as the interpretation of CP0.Config[5:0] registers has 
been architectural and mandatory, and that for a reason.  It's only legacy 
MIPS I-IV processors that should require special attention here.

  Maciej