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Date: Sat, 22 Aug 2020 13:48:13 +0900 From: Daniel Palmer <daniel@...f.com> To: Mark-PK Tsai <mark-pk.tsai@...iatek.com> Cc: Marc Zyngier <maz@...nel.org>, alix.wu@...iatek.com, DTML <devicetree@...r.kernel.org>, Jason Cooper <jason@...edaemon.net>, linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>, linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org, Matthias Brugger <matthias.bgg@...il.com>, Rob Herring <robh+dt@...nel.org>, Thomas Gleixner <tglx@...utronix.de>, yj.chiang@...iatek.com Subject: Re: [PATCH v2 1/2] irqchip: irq-mst: Add MStar interrupt controller support Hi Mark-PK, On Thu, 20 Aug 2020 at 00:38, Mark-PK Tsai <mark-pk.tsai@...iatek.com> wrote: > > Add MStar interrupt controller support using hierarchy irq > domain. > > Signed-off-by: Mark-PK Tsai <mark-pk.tsai@...iatek.com> I've integrated this version into my MStar/SigmaStar tree and tested on an MStar MSC313E based board (BreadBee) and I'm happy to say it seems to be working: $ cat /proc/interrupts CPU0 17: 1219 GIC-0 29 Level arch_timer 18: 0 GIC-0 30 Level arch_timer 21: 0 GIC-0 42 Level arm-pmu 24: 0 mst-intc 44 Level 1f002400.rtc 30: 0 mst-intc 2 Level 1f006000.wdt 31: 0 mst-intc 0 Level 1f006040.timer 32: 0 mst-intc 1 Level 1f006080.timer 33: 0 mst-intc 12 Level 1f0060c0.timer 34: 0 mst-intc 40 Level 1f200400.bdma 35: 3977 mst-intc 41 Level 1f200400.bdma 37: 196 mst-intc 34 Level ttyS0 40: 0 mst-intc 30 Level soc:usbphy@0 <snip> So here's my tested by: Tested-by: Daniel Palmer <daniel@...ngy.jp> I don't think your series contained an update to MAINTAINERS. If/when you add this could you add my address above as a reviewer so I'm in the loop if anyone makes changes to this going forward? Thanks, Daniel
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