lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Sun, 23 Aug 2020 10:00:51 +0800
From:   Shawn Guo <shawnguo@...nel.org>
To:     Krzysztof Kozlowski <krzk@...nel.org>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        Anson Huang <Anson.Huang@....com>,
        Li Yang <leoyang.li@....com>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 4/4] arm64: dts: imx8mm-var-som-symphony: Add
 Variscite Symphony board with VAR-SOM-MX8MM

On Mon, Aug 17, 2020 at 09:01:20AM +0200, Krzysztof Kozlowski wrote:
> Add a DTS for Variscite Symphony evaluation kit with VAR-SOM-MX8MM
> System on Module.
> 
> Signed-off-by: Krzysztof Kozlowski <krzk@...nel.org>
> 
> ---
> 
> Changes since v1:
> 1. Remove duplicated "leds" node,
> 2. Fix heartbeat to active low,
> 3. Add nxp,ptn5150 extcon.
> ---
>  arch/arm64/boot/dts/freescale/Makefile        |   1 +
>  .../dts/freescale/imx8mm-var-som-symphony.dts | 248 ++++++++++++++++++
>  2 files changed, 249 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
> 
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index a39f0a1723e0..dcfb8750cd78 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
>  
>  dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
> new file mode 100644
> index 000000000000..2d3c30ac5e04
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
> @@ -0,0 +1,248 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2020 Krzysztof Kozlowski <krzk@...nel.org>
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mm-var-som.dtsi"
> +
> +/ {
> +	model = "Variscite VAR-SOM-MX8MM Symphony evaluation board";
> +	compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm";
> +
> +	reg_usdhc2_vmmc: regulator-1 {

regulator-usdhc2-vmmc

> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> +		regulator-name = "VSD_3V3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
> +
> +	reg_usb_otg2_vbus: regulator-2 {

regulator-usb-otg2-vbus

> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>;
> +		regulator-name = "usb_otg2_vbus";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +
> +		back {
> +			label = "Back";
> +			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_BACK>;
> +		};
> +
> +		home {
> +			label = "Home";
> +			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_HOME>;
> +		};
> +
> +		menu {
> +			label = "Menu";
> +			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_MENU>;
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		heartbeat {
> +			label = "Heartbeat";
> +			gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +};
> +
> +&ethphy {
> +	reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
> +};
> +
> +&i2c2 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c2>;
> +	status = "okay";
> +
> +	pca9534: gpio@20 {
> +		compatible = "nxp,pca9534";
> +		reg = <0x20>;
> +		gpio-controller;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_pca9534>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
> +		#gpio-cells = <2>;
> +		wakeup-source;
> +
> +		/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
> +		usb3-sata-sel-hog {
> +			gpio-hog;
> +			gpios = <4 GPIO_ACTIVE_HIGH>;
> +			output-low;
> +			line-name = "usb3_sata_sel";
> +		};
> +
> +		som-vselect-hog {
> +			gpio-hog;
> +			gpios = <6 GPIO_ACTIVE_HIGH>;
> +			output-low;
> +			line-name = "som_vselect";
> +		};
> +
> +		enet-sel-hog {
> +			gpio-hog;
> +			gpios = <7 GPIO_ACTIVE_HIGH>;
> +			output-low;
> +			line-name = "enet_sel";
> +		};
> +	};
> +
> +	extcon_usbotg1: typec@3d {
> +		compatible = "nxp,ptn5150";
> +		reg = <0x3d>;
> +		int-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_ptn5150>;
> +		status = "okay";
> +	};
> +};
> +
> +&i2c3 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c3>;
> +	status = "okay";
> +
> +	/* Capacitive touch controller */
> +	ft5x06_ts: touchscreen@38 {
> +		compatible = "edt,edt-ft5406";
> +		reg = <0x38>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_captouch>;
> +		interrupt-parent = <&gpio5>;
> +		interrupts = <4 GPIO_ACTIVE_HIGH>;
> +
> +		touchscreen-size-x = <800>;
> +		touchscreen-size-y = <480>;
> +		touchscreen-inverted-x;
> +		touchscreen-inverted-y;
> +	};
> +
> +	rtc@68 {
> +		compatible = "dallas,ds1337";
> +		reg = <0x68>;
> +		wakeup-source;
> +	};
> +};
> +
> +/* Header */
> +&uart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	status = "okay";
> +};
> +
> +/* Header */
> +&uart3 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart3>;
> +	status = "okay";
> +};
> +
> +&usbotg1 {
> +	disable-over-current;
> +	extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
> +};
> +
> +&usbotg2 {
> +	dr_mode = "host";
> +	vbus-supply = <&reg_usb_otg2_vbus>;
> +	srp-disable;
> +	hnp-disable;
> +	adp-disable;
> +	disable-over-current;
> +	/delete-property/ usb-role-switch;
> +	/*
> +	 * FIXME: having USB2 enabled hangs the boot just after:
> +	 * [    1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller
> +	 * [    1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1
> +	 * [    1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
> +	 * [    1.977203] hub 1-0:1.0: USB hub found
> +	 * [    1.980987] hub 1-0:1.0: 1 port detected
> +	 */
> +	status = "disabled";
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";

Drop this.

Shawn

> +
> +	pinctrl_captouch: captouchgrp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x16
> +		>;
> +	};
> +
> +	pinctrl_gpio_led: gpioledgrp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
> +		>;
> +	};
> +
> +	pinctrl_i2c2: i2c2grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
> +			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
> +		>;
> +	};
> +
> +	pinctrl_pca9534: pca9534grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16
> +		>;
> +	};
> +
> +	pinctrl_ptn5150: ptn5150grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x16
> +		>;
> +	};
> +
> +	pinctrl_reg_usb_otg2_vbus: regusbotg2vbusgrp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1		0x16
> +		>;
> +	};
> +
> +	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
> +		>;
> +	};
> +
> +	pinctrl_uart1: uart1grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
> +			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
> +		>;
> +	};
> +
> +	pinctrl_uart3: uart3grp {
> +		fsl,pins = <
> +			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
> +			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
> +		>;
> +	};
> +};
> -- 
> 2.17.1
> 

Powered by blists - more mailing lists