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Message-ID: <202008250356.wRqEkppM%lkp@intel.com>
Date: Tue, 25 Aug 2020 04:03:08 +0800
From: kernel test robot <lkp@...el.com>
To: Lars Povlsen <lars.povlsen@...rochip.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
Adrian Hunter <adrian.hunter@...el.com>,
SoC Team <soc@...nel.org>
Cc: kbuild-all@...ts.01.org, Lars Povlsen <lars.povlsen@...rochip.com>,
Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Alexandre Belloni <alexandre.belloni@...tlin.com>
Subject: Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
Hi Lars,
I love your patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v5.9-rc2 next-20200824]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Lars-Povlsen/mmc-Adding-support-for-Microchip-Sparx5-SoC/20200824-231355
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
>> drivers/mmc/host/sdhci-of-sparx5.c:158:5: warning: no previous prototype for 'sdhci_sparx5_probe' [-Wmissing-prototypes]
158 | int sdhci_sparx5_probe(struct platform_device *pdev)
| ^~~~~~~~~~~~~~~~~~
# https://github.com/0day-ci/linux/commit/dd46278eff00cacc114d229429f51fbdbcb2e8f2
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Lars-Povlsen/mmc-Adding-support-for-Microchip-Sparx5-SoC/20200824-231355
git checkout dd46278eff00cacc114d229429f51fbdbcb2e8f2
vim +/sdhci_sparx5_probe +158 drivers/mmc/host/sdhci-of-sparx5.c
157
> 158 int sdhci_sparx5_probe(struct platform_device *pdev)
159 {
160 int ret;
161 const char *syscon = "microchip,sparx5-cpu-syscon";
162 struct sdhci_host *host;
163 struct sdhci_pltfm_host *pltfm_host;
164 struct sdhci_sparx5_data *sdhci_sparx5;
165 struct device_node *np = pdev->dev.of_node;
166 u32 value;
167 u32 extra;
168
169 host = sdhci_pltfm_init(pdev, &sdhci_sparx5_pdata,
170 sizeof(*sdhci_sparx5));
171
172 if (IS_ERR(host))
173 return PTR_ERR(host);
174
175 /*
176 * extra adma table cnt for cross 128M boundary handling.
177 */
178 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
179 if (extra > SDHCI_MAX_SEGS)
180 extra = SDHCI_MAX_SEGS;
181 host->adma_table_cnt += extra;
182
183 pltfm_host = sdhci_priv(host);
184 sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
185 sdhci_sparx5->host = host;
186
187 pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
188 if (IS_ERR(pltfm_host->clk)) {
189 ret = PTR_ERR(pltfm_host->clk);
190 dev_err(&pdev->dev, "failed to get core clk: %d\n", ret);
191 goto free_pltfm;
192 }
193 ret = clk_prepare_enable(pltfm_host->clk);
194 if (ret)
195 goto free_pltfm;
196
197 if (!of_property_read_u32(np, "microchip,clock-delay", &value) &&
198 (value > 0 && value <= MSHC_DLY_CC_MAX))
199 sdhci_sparx5->delay_clock = value;
200
201 sdhci_get_of_property(pdev);
202
203 ret = mmc_of_parse(host->mmc);
204 if (ret)
205 goto err_clk;
206
207 sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon);
208 if (IS_ERR(sdhci_sparx5->cpu_ctrl)) {
209 dev_err(&pdev->dev, "No CPU syscon regmap !\n");
210 ret = PTR_ERR(sdhci_sparx5->cpu_ctrl);
211 goto err_clk;
212 }
213
214 if (sdhci_sparx5->delay_clock >= 0)
215 sparx5_set_delay(host, sdhci_sparx5->delay_clock);
216
217 if (!mmc_card_is_removable(host->mmc)) {
218 /* Do a HW reset of eMMC card */
219 sdhci_sparx5_reset_emmc(host);
220 /* Update EMMC_CTRL */
221 sdhci_sparx5_set_emmc(host);
222 /* If eMMC, disable SD and SDIO */
223 host->mmc->caps2 |= (MMC_CAP2_NO_SDIO|MMC_CAP2_NO_SD);
224 }
225
226 ret = sdhci_add_host(host);
227 if (ret)
228 goto err_clk;
229
230 /* Set AXI bus master to use un-cached access (for DMA) */
231 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) &&
232 IS_ENABLED(CONFIG_DMA_DECLARE_COHERENT))
233 sparx5_set_cacheable(host, ACP_CACHE_FORCE_ENA);
234
235 pr_debug("%s: SDHC version: 0x%08x\n",
236 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION));
237 pr_debug("%s: SDHC type: 0x%08x\n",
238 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE));
239
240 return ret;
241
242 err_clk:
243 clk_disable_unprepare(pltfm_host->clk);
244 free_pltfm:
245 sdhci_pltfm_free(pdev);
246 return ret;
247 }
248
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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