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Date: Tue, 25 Aug 2020 19:13:57 +0200 From: Jernej Skrabec <jernej.skrabec@...l.net> To: mripard@...nel.org, wens@...e.org Cc: mchehab@...nel.org, robh+dt@...nel.org, linux-media@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com Subject: [PATCH 2/3] ARM: dts: sun8i: r40: Add IR nodes Allwinner R40 has two IR cores, add nodes for them. Signed-off-by: Jernej Skrabec <jernej.skrabec@...l.net> --- arch/arm/boot/dts/sun8i-r40.dtsi | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d481fe7989b8..dff9a3dc1fba 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -513,6 +513,16 @@ i2c4_pins: i2c4-pins { function = "i2c4"; }; + ir0_pins: ir0-pins { + pins = "PB4"; + function = "ir0"; + }; + + ir1_pins: ir1-pins { + pins = "PB23"; + function = "ir1"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -591,6 +601,32 @@ wdt: watchdog@...0c90 { clocks = <&osc24M>; }; + ir0: ir@...1800 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21800 0x400>; + pinctrl-0 = <&ir0_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; + clock-names = "apb", "ir"; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_IR0>; + status = "disabled"; + }; + + ir1: ir@...1c00 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21c00 0x400>; + pinctrl-0 = <&ir1_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; + clock-names = "apb", "ir"; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_IR1>; + status = "disabled"; + }; + ths: thermal-sensor@...4c00 { compatible = "allwinner,sun8i-r40-ths"; reg = <0x01c24c00 0x100>; -- 2.28.0
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