linux-kernel - Re: [PATCH v5 1/5] dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings

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Message-ID: <20200825190921.GA1144515@bogus>
Date:   Tue, 25 Aug 2020 13:09:21 -0600
From:   Rob Herring <robh@...nel.org>
To:     Grzegorz Jaszczyk <grzegorz.jaszczyk@...aro.org>
Cc:     tglx@...utronix.de, maz@...nel.org, devicetree@...r.kernel.org,
        jason@...edaemon.net, robh+dt@...nel.org, s-anna@...com,
        linux-omap@...r.kernel.org, david@...hnology.com,
        linux-arm-kernel@...ts.infradead.org,
        Roger Quadros <rogerq@...com>, praneeth@...com,
        "Andrew F . Davis" <afd@...com>, lee.jones@...aro.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 1/5] dt-bindings: irqchip: Add PRU-ICSS interrupt
 controller bindings

On Mon, 17 Aug 2020 15:40:09 +0200, Grzegorz Jaszczyk wrote:
> From: Suman Anna <s-anna@...com>
> 
> The Programmable Real-Time Unit and Industrial Communication Subsystem
> (PRU-ICSS or simply PRUSS) contains an interrupt controller (INTC) that
> can handle various system input events and post interrupts back to the
> device-level initiators. The INTC can support up to 64 input events on
> most SoCs with individual control configuration and h/w prioritization.
> These events are mapped onto 10 output interrupt lines through two levels
> of many-to-one mapping support. Different interrupt lines are routed to
> the individual PRU cores or to the host CPU or to other PRUSS instances.
> 
> The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP,
> commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide
> a higher number of host interrupts (20 vs 10) and can handle an increased
> number of input events (160 vs 64) from various SoC interrupt sources.
> 
> Add the bindings document for these interrupt controllers on all the
> applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x
> and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci
> architecture based OMAPL138 SoCs, and the K3 architecture based AM65x
> and J721E SoCs.
> 
> Signed-off-by: Suman Anna <s-anna@...com>
> Signed-off-by: Andrew F. Davis <afd@...com>
> Signed-off-by: Roger Quadros <rogerq@...com>
> Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@...aro.org>
> ---
> v4->v5:
> - Fix typo in commit description.
> - Update interrupt-cells description regarding each cells meaning.
> v3->v4:
> - Drop allOf references to interrupt-controller.yaml and
>   interrupts.yaml.
> - Drop items descriptions and use only maxItems: 1 as suggested by Rob.
> - Convert irqs-reserved property from uint8-array to bitmask.
> - Minor descriptions updates.
> - Change interrupt-cells to 3 in order to provide 2-level mapping
>   description for interrupts routed to the main CPU (as Marc requested).
> - Merge the irqs-reserved and irqs-shared to one property since they
>   can be handled by one logic.
> - Drop reviewed-by due to introduced changes.
> - Add another example illustrating irqs-reserved property usage.
> v2->v3:
> - Convert dt-binding to YAML
> v1->v2:
> - https://patchwork.kernel.org/patch/11069767/
> 
> update irq-pruss-intc binding
> ---
>  .../interrupt-controller/ti,pruss-intc.yaml        | 158 +++++++++++++++++++++
>  1 file changed, 158 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
> 

Reviewed-by: Rob Herring <robh@...nel.org>