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Date: Tue, 25 Aug 2020 11:30:15 +0200 From: Christophe Leroy <christophe.leroy@...roup.eu> To: Ravi Bangoria <ravi.bangoria@...ux.ibm.com>, mpe@...erman.id.au, christophe.leroy@....fr Cc: mikey@...ling.org, paulus@...ba.org, naveen.n.rao@...ux.vnet.ibm.com, pedromfc@...ux.ibm.com, rogealve@...ux.ibm.com, jniethe5@...il.com, linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH v5 4/8] powerpc/watchpoint: Move DAWR detection logic outside of hw_breakpoint.c Le 25/08/2020 à 06:36, Ravi Bangoria a écrit : > Power10 hw has multiple DAWRs but hw doesn't tell which DAWR caused > the exception. So we have a sw logic to detect that in hw_breakpoint.c. > But hw_breakpoint.c gets compiled only with CONFIG_HAVE_HW_BREAKPOINT=Y. > Move DAWR detection logic outside of hw_breakpoint.c so that it can be > reused when CONFIG_HAVE_HW_BREAKPOINT is not set. > > Signed-off-by: Ravi Bangoria <ravi.bangoria@...ux.ibm.com> > --- > arch/powerpc/include/asm/hw_breakpoint.h | 8 + > arch/powerpc/kernel/Makefile | 3 +- > arch/powerpc/kernel/hw_breakpoint.c | 159 +---------------- > .../kernel/hw_breakpoint_constraints.c | 162 ++++++++++++++++++ > 4 files changed, 174 insertions(+), 158 deletions(-) > create mode 100644 arch/powerpc/kernel/hw_breakpoint_constraints.c > [...] > diff --git a/arch/powerpc/kernel/hw_breakpoint_constraints.c b/arch/powerpc/kernel/hw_breakpoint_constraints.c > new file mode 100644 > index 000000000000..867ee4aa026a > --- /dev/null > +++ b/arch/powerpc/kernel/hw_breakpoint_constraints.c > @@ -0,0 +1,162 @@ [...] > + > +static int cache_op_size(void) > +{ > +#ifdef __powerpc64__ > + return ppc64_caches.l1d.block_size; > +#else > + return L1_CACHE_BYTES; > +#endif > +} You've got l1_dcache_bytes() in arch/powerpc/include/asm/cache.h to do that. > + > +void wp_get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr, > + int *type, int *size, unsigned long *ea) > +{ > + struct instruction_op op; > + > + if (__get_user_instr_inatomic(*instr, (void __user *)regs->nip)) > + return; > + > + analyse_instr(&op, regs, *instr); > + *type = GETTYPE(op.type); > + *ea = op.ea; > +#ifdef __powerpc64__ > + if (!(regs->msr & MSR_64BIT)) > + *ea &= 0xffffffffUL; > +#endif This #ifdef is unneeded, it should build fine on a 32 bits too. > + > + *size = GETSIZE(op.type); > + if (*type == CACHEOP) { > + *size = cache_op_size(); > + *ea &= ~(*size - 1); > + } else if (*type == LOAD_VMX || *type == STORE_VMX) { > + *ea &= ~(*size - 1); > + } > +} > Christophe
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