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Date: Tue, 25 Aug 2020 15:18:05 +0100 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> To: Geert Uytterhoeven <geert+renesas@...der.be>, Joerg Roedel <joro@...tes.org>, Rob Herring <robh+dt@...nel.org>, Magnus Damm <magnus.damm@...il.com>, Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>, iommu@...ts.linux-foundation.org, linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org Cc: linux-kernel@...r.kernel.org, Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, Prabhakar <prabhakar.csengg@...il.com> Subject: [PATCH 2/2] ARM: dts: r8a7742: Add IPMMU DT nodes Add the five IPMMU instances found in the r8a7742 to DT with a disabled status. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@...esas.com> --- arch/arm/boot/dts/r8a7742.dtsi | 48 ++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 0fc52b27ae64..c62e26876f95 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -412,6 +412,54 @@ #thermal-sensor-cells = <0>; }; + ipmmu_sy0: iommu@...80000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: iommu@...90000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: iommu@...40000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: iommu@...80000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: iommu@...51000 { + compatible = "renesas,ipmmu-r8a7742", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + icram0: sram@...a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; -- 2.17.1
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